fenpin_36.v

来自「在公司做的TCM编解码程序」· Verilog 代码 · 共 20 行

module fenpin_36(bs,fsout);
input bs;
output fsout;

reg fsout;
reg [5:0] temp;

always@(posedge bs)
begin
     if(temp==35)begin
        fsout=1;
        temp=0;
     end
     else begin
        fsout=0;
        temp=temp+1;
     end
end
endmodule