seri_para.v

来自「在公司做的TCM编解码程序」· Verilog 代码 · 共 24 行

module	seri_para(series,bs,fs,parallel);
input	series,bs,fs;		//4kHz count
output	[11:0]parallel;

reg		[11:0]parallel,rega;
reg		[4:0] n;

always@	(posedge bs)
	rega[n]=series;

always@(posedge fs or negedge bs )
begin
	if(fs==1)
	begin
		n=11;
//		parallel=rega;
	end
	
	else if(bs==0) begin
		n=n-1;
	end
	parallel=rega;	
end
endmodule