tcm0201.qsf

在公司做的TCM编解码程序

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		TCM0201_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:03:21  SEPTEMBER 12, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VERILOG_FILE fenpin_36.v
set_global_assignment -name VERILOG_FILE bus2line.v
set_global_assignment -name VHDL_FILE parallel_series.vhd
set_global_assignment -name VHDL_FILE series_parallel.vhd
set_global_assignment -name BDF_FILE change.bdf
set_global_assignment -name VHDL_FILE DIDQ.vhd
set_global_assignment -name BDF_FILE 3IN1.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE TCM0201.vwf
set_global_assignment -name BDF_FILE TCM0201.bdf
set_global_assignment -name BDF_FILE DEVIDE.bdf
set_global_assignment -name VERILOG_FILE para_out12.v
set_global_assignment -name VERILOG_FILE seri_para.v
set_global_assignment -name VHDL_FILE fs_out3.vhd
set_global_assignment -name VHDL_FILE series_para_store.vhd
set_global_assignment -name VERILOG_FILE parallel_12out.v
set_global_assignment -name VERILOG_FILE count.v

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_46 -to B5
set_location_assignment PIN_125 -to CLK1
set_location_assignment PIN_36 -to DI
set_location_assignment PIN_38 -to DQ
set_location_assignment PIN_127 -to RST
set_location_assignment PIN_35 -to Y1
set_location_assignment PIN_37 -to Y2
set_location_assignment PIN_39 -to Y3
set_location_assignment PIN_137 -to 3IN1
set_location_assignment PIN_71 -to NRZIN
set_location_assignment PIN_74 -to BS/3
set_location_assignment PIN_2 -to BBS/2
set_location_assignment PIN_133 -to BS
set_location_assignment PIN_100 -to FS_IN
set_location_assignment PIN_99 -to FS_OUT
set_location_assignment PIN_140 -to fsout
set_location_assignment PIN_40 -to addr[0]
set_location_assignment PIN_41 -to addr[1]
set_location_assignment PIN_43 -to addr[2]
set_location_assignment PIN_101 -to data_out[0]
set_location_assignment PIN_102 -to data_out[1]
set_location_assignment PIN_103 -to data_out[2]
set_location_assignment PIN_106 -to data_out[3]
set_location_assignment PIN_107 -to data_out[4]
set_location_assignment PIN_108 -to data_out[5]
set_location_assignment PIN_109 -to data_out[6]
set_location_assignment PIN_110 -to data_out[7]
set_location_assignment PIN_111 -to data_out[8]
set_location_assignment PIN_112 -to data_out[9]
set_location_assignment PIN_113 -to data_out[10]
set_location_assignment PIN_116 -to data_out[11]
set_location_assignment PIN_47 -to fs_out3
set_location_assignment PIN_62 -to out1
set_location_assignment PIN_63 -to out2
set_location_assignment PIN_65 -to out3
set_location_assignment PIN_66 -to out4
set_location_assignment PIN_67 -to out5
set_location_assignment PIN_68 -to out6
set_location_assignment PIN_69 -to out7
set_location_assignment PIN_75 -to out8
set_location_assignment PIN_78 -to out9
set_location_assignment PIN_79 -to out10
set_location_assignment PIN_81 -to out11
set_location_assignment PIN_83 -to out12
set_location_assignment PIN_34 -to A0
set_location_assignment PIN_45 -to A1
set_location_assignment PIN_47 -to A2
set_location_assignment PIN_62 -to A3
set_location_assignment PIN_63 -to A4
set_location_assignment PIN_65 -to A5
set_location_assignment PIN_66 -to A6
set_location_assignment PIN_68 -to B0
set_location_assignment PIN_70 -to B1
set_location_assignment PIN_72 -to B2
set_location_assignment PIN_75 -to B3
set_location_assignment PIN_79 -to B4
set_location_assignment PIN_81 -to B6

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name TOP_LEVEL_ENTITY TCM0201

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPM3256ATC144-10"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_instance_assignment -name IO_STANDARD LVTTL -to DQ
set_instance_assignment -name IO_STANDARD LVTTL -to BBS
set_instance_assignment -name IO_STANDARD LVTTL -to DQ1
set_instance_assignment -name IO_STANDARD LVTTL -to FS
set_instance_assignment -name IO_STANDARD LVTTL -to FS_IN
set_instance_assignment -name IO_STANDARD LVTTL -to B5
set_instance_assignment -name IO_STANDARD LVTTL -to fs_out3

# Assembler Assignments
# =====================
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"