para_out12.v

在公司做的TCM编解码程序

module para_out12(addr,reg1,reg2,reg3,data_out);
input [2:0]addr;
input [11:0]reg1,reg2,reg3;
output [11:0]data_out;

reg [11:0]data_out;
wire [11:0]reg4,reg5,reg6;
assign reg4=reg1;
assign reg5=reg2;
assign reg6=reg3;

always@(addr)
	case(addr)
	3'b100:data_out=reg4;
	3'b101:data_out=reg5;
	3'b110:data_out=reg6;
	default:data_out=12'bz;
	endcase
endmodule