tcm0201.fit.eqn

在公司做的TCM编解码程序

L1L6_p2_out = !FS_IN & L1L6;
L1L6_p3_out = M1_parallel[10] & L1L6;
L1L6_or_out = L1L6_p1_out # L1L6_p2_out # L1L6_p3_out;
L1L6 = L1L6_or_out;


--S1_fsout is 3IN12:inst7|fenpin_36:inst1|fsout at LC14
S1_fsout_p1_out = S1_temp[5] & !S1_temp[4] & !S1_temp[3] & !S1_temp[2] & S1_temp[1] & S1_temp[0];
S1_fsout_or_out = S1_fsout_p1_out;
S1_fsout_reg_input = S1_fsout_or_out;
S1_fsout = DFFE(S1_fsout_reg_input, R2_3, , , );


--L2L41 is change:inst4|parallel_series:inst5|digit_out~12 at LC178
L2L41_p0_out = L1_n[0] & !L1_n[1] & L2_n[3] & !L2_n[2] & !FS_IN & L2L01;
L2L41_p1_out = L2L7 & !L1_n[0] & L1_n[1] & !L2_n[3] & L2_n[2] & !FS_IN;
L2L41_p2_out = L1_n[0] & L1_n[1] & !L2_n[3] & L2_n[2] & !FS_IN & L2L8;
L2L41_p3_out = !L1_n[0] & !L1_n[1] & !L2_n[3] & L2_n[2] & !FS_IN & L2L5;
L2L41_p4_out = L1_n[0] & !L1_n[1] & !L2_n[3] & L2_n[2] & !FS_IN & L2L6;
L2L41_or_out = L2L61 # L2L41_p0_out # L2L41_p1_out # L2L41_p2_out # L2L41_p3_out # L2L41_p4_out;
L2L41 = L2L41_or_out;


--L2_digit_out is change:inst4|parallel_series:inst5|digit_out at LC61
L2_digit_out_p1_out = L2L51 & !L2L41;
L2_digit_out_or_out = L2_digit_out_p1_out;
L2_digit_out_reg_input = !(L2_digit_out_or_out);
L2_digit_out = DFFE(L2_digit_out_reg_input, !D1_inst2, , , );


--C1_inst1 is CODEandIE:inst2|inst1 at LC109
C1_inst1_or_out = L2_digit_out;
C1_inst1_reg_input = C1_inst1_or_out;
C1_inst1 = DFFE(C1_inst1_reg_input, !D1_inst2, , , );


--L1_digit_out is change:inst4|parallel_series:inst|digit_out at LC33
L1_digit_out_p1_out = L1L61 & L1L41 & L1L51;
L1_digit_out_or_out = L1_digit_out_p1_out;
L1_digit_out_reg_input = !(L1_digit_out_or_out);
L1_digit_out = DFFE(L1_digit_out_reg_input, !D1_inst2, , , );


--C1_inst8 is CODEandIE:inst2|inst8 at LC35
C1_inst8_or_out = L1_digit_out;
C1_inst8_reg_input = C1_inst8_or_out;
C1_inst8 = DFFE(C1_inst8_reg_input, !D1_inst2, , , );


--C1_inst4 is CODEandIE:inst2|inst4 at LC59
C1_inst4_or_out = C1_inst1;
C1_inst4_reg_input = C1_inst4_or_out;
C1_inst4 = DFFE(C1_inst4_reg_input, !D1_inst2, , , );


--C1L3 is CODEandIE:inst2|inst7~9 at LC64
C1L3_or_out = C1_inst4;
C1L3 = C1_inst1 $ C1L3_or_out;


--F1_inst9 is 3IN12:inst7|inst9 at LC60
F1_inst9_p1_out = !C1_inst4 & K1_8 & K1_9;
F1_inst9_or_out = F1_inst9_p1_out;
F1_inst9_reg_input = !(F1_inst9_or_out);
F1_inst9 = DFFE(F1_inst9_reg_input, R2_3, , , );


--F1_inst7 is 3IN12:inst7|inst7 at LC63
F1_inst7_p1_out = !C1_inst8 & K1_8 & K1_9;
F1_inst7_or_out = F1_inst7_p1_out;
F1_inst7_reg_input = !(F1_inst7_or_out);
F1_inst7 = DFFE(F1_inst7_reg_input, R2_3, , , );


--F1_inst8 is 3IN12:inst7|inst8 at LC62
F1_inst8_p1_out = C1_inst1 & !C1_inst4;
F1_inst8_p2_out = !C1_inst1 & C1_inst4;
F1_inst8_or_out = F1_inst8_p1_out # F1_inst8_p2_out # !C1L5;
F1_inst8_reg_input = F1_inst8_or_out;
F1_inst8 = DFFE(F1_inst8_reg_input, R2_3, , , );


--G1_rega[10] is series_para_store:inst19|rega[10] at LC39
G1_rega[10]_p1_out = !C1L5 & Q2_dffs[1] & Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G1_rega[10];
G1_rega[10]_p2_out = Q2_dffs[1] & Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G1_rega[10] & C1_inst8;
G1_rega[10]_p4_out = C1L5 & Q2_dffs[1] & Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & G1_rega[10] & !C1_inst8;
G1_rega[10]_or_out = G1_rega[10]_p1_out # G1_rega[10]_p2_out # G1_rega[10]_p4_out;
G1_rega[10]_reg_input = G1_rega[10]_or_out;
G1_rega[10] = TFFE(G1_rega[10]_reg_input, D1_inst2, , , );


--G1_rega[9] is series_para_store:inst19|rega[9] at LC40
G1_rega[9]_p1_out = !C1L5 & Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & !Q2_dffs[1] & !G1_rega[9];
G1_rega[9]_p2_out = Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & !Q2_dffs[1] & !G1_rega[9] & C1_inst8;
G1_rega[9]_p4_out = C1L5 & Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & !Q2_dffs[1] & G1_rega[9] & !C1_inst8;
G1_rega[9]_or_out = G1_rega[9]_p1_out # G1_rega[9]_p2_out # G1_rega[9]_p4_out;
G1_rega[9]_reg_input = G1_rega[9]_or_out;
G1_rega[9] = TFFE(G1_rega[9]_reg_input, D1_inst2, , , );


--G1_rega[8] is series_para_store:inst19|rega[8] at LC42
G1_rega[8]_p1_out = !C1L5 & !Q2_dffs[1] & Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G1_rega[8];
G1_rega[8]_p2_out = !Q2_dffs[1] & Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G1_rega[8] & C1_inst8;
G1_rega[8]_p4_out = C1L5 & !Q2_dffs[1] & Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & G1_rega[8] & !C1_inst8;
G1_rega[8]_or_out = G1_rega[8]_p1_out # G1_rega[8]_p2_out # G1_rega[8]_p4_out;
G1_rega[8]_reg_input = G1_rega[8]_or_out;
G1_rega[8] = TFFE(G1_rega[8]_reg_input, D1_inst2, , , );


--G1_rega[7] is series_para_store:inst19|rega[7] at LC43
G1_rega[7]_p1_out = !C1L5 & Q2_dffs[0] & Q2_dffs[1] & !Q2_dffs[3] & Q2_dffs[2] & !G1_rega[7];
G1_rega[7]_p2_out = Q2_dffs[0] & Q2_dffs[1] & !Q2_dffs[3] & Q2_dffs[2] & !G1_rega[7] & C1_inst8;
G1_rega[7]_p4_out = C1L5 & Q2_dffs[0] & Q2_dffs[1] & !Q2_dffs[3] & Q2_dffs[2] & G1_rega[7] & !C1_inst8;
G1_rega[7]_or_out = G1_rega[7]_p1_out # G1_rega[7]_p2_out # G1_rega[7]_p4_out;
G1_rega[7]_reg_input = G1_rega[7]_or_out;
G1_rega[7] = TFFE(G1_rega[7]_reg_input, D1_inst2, , , );


--G1_rega[6] is series_para_store:inst19|rega[6] at LC41
G1_rega[6]_p1_out = !C1L5 & Q2_dffs[1] & !Q2_dffs[0] & !Q2_dffs[3] & Q2_dffs[2] & !G1_rega[6];
G1_rega[6]_p2_out = Q2_dffs[1] & !Q2_dffs[0] & !Q2_dffs[3] & Q2_dffs[2] & !G1_rega[6] & C1_inst8;
G1_rega[6]_p4_out = C1L5 & Q2_dffs[1] & !Q2_dffs[0] & !Q2_dffs[3] & Q2_dffs[2] & G1_rega[6] & !C1_inst8;
G1_rega[6]_or_out = G1_rega[6]_p1_out # G1_rega[6]_p2_out # G1_rega[6]_p4_out;
G1_rega[6]_reg_input = G1_rega[6]_or_out;
G1_rega[6] = TFFE(G1_rega[6]_reg_input, D1_inst2, , , );


--G1_rega[5] is series_para_store:inst19|rega[5] at LC45
G1_rega[5]_p1_out = !C1L5 & Q2_dffs[0] & !Q2_dffs[1] & !Q2_dffs[3] & Q2_dffs[2] & !G1_rega[5];
G1_rega[5]_p2_out = Q2_dffs[0] & !Q2_dffs[1] & !Q2_dffs[3] & Q2_dffs[2] & !G1_rega[5] & C1_inst8;
G1_rega[5]_p4_out = C1L5 & Q2_dffs[0] & !Q2_dffs[1] & !Q2_dffs[3] & Q2_dffs[2] & G1_rega[5] & !C1_inst8;
G1_rega[5]_or_out = G1_rega[5]_p1_out # G1_rega[5]_p2_out # G1_rega[5]_p4_out;
G1_rega[5]_reg_input = G1_rega[5]_or_out;
G1_rega[5] = TFFE(G1_rega[5]_reg_input, D1_inst2, , , );


--G1_rega[4] is series_para_store:inst19|rega[4] at LC34
G1_rega[4]_p1_out = !C1L5 & !Q2_dffs[1] & !Q2_dffs[0] & !Q2_dffs[3] & Q2_dffs[2] & !G1_rega[4];
G1_rega[4]_p2_out = !Q2_dffs[1] & !Q2_dffs[0] & !Q2_dffs[3] & Q2_dffs[2] & !G1_rega[4] & C1_inst8;
G1_rega[4]_p4_out = C1L5 & !Q2_dffs[1] & !Q2_dffs[0] & !Q2_dffs[3] & Q2_dffs[2] & G1_rega[4] & !C1_inst8;
G1_rega[4]_or_out = G1_rega[4]_p1_out # G1_rega[4]_p2_out # G1_rega[4]_p4_out;
G1_rega[4]_reg_input = G1_rega[4]_or_out;
G1_rega[4] = TFFE(G1_rega[4]_reg_input, D1_inst2, , , );


--G1_rega[3] is series_para_store:inst19|rega[3] at LC250
G1_rega[3]_p1_out = !C1L5 & !Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & Q2_dffs[1] & !G1_rega[3];
G1_rega[3]_p2_out = !Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & Q2_dffs[1] & !G1_rega[3] & C1_inst8;
G1_rega[3]_p4_out = C1L5 & !Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & Q2_dffs[1] & G1_rega[3] & !C1_inst8;
G1_rega[3]_or_out = G1_rega[3]_p1_out # G1_rega[3]_p2_out # G1_rega[3]_p4_out;
G1_rega[3]_reg_input = G1_rega[3]_or_out;
G1_rega[3] = TFFE(G1_rega[3]_reg_input, D1_inst2, , , );


--G1_rega[2] is series_para_store:inst19|rega[2] at LC251
G1_rega[2]_p1_out = !C1L5 & Q2_dffs[1] & !Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G1_rega[2];
G1_rega[2]_p2_out = Q2_dffs[1] & !Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G1_rega[2] & C1_inst8;
G1_rega[2]_p4_out = C1L5 & Q2_dffs[1] & !Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & G1_rega[2] & !C1_inst8;
G1_rega[2]_or_out = G1_rega[2]_p1_out # G1_rega[2]_p2_out # G1_rega[2]_p4_out;
G1_rega[2]_reg_input = G1_rega[2]_or_out;
G1_rega[2] = TFFE(G1_rega[2]_reg_input, D1_inst2, , , );


--G1_rega[1] is series_para_store:inst19|rega[1] at LC252
G1_rega[1]_p1_out = !C1L5 & !Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & !Q2_dffs[1] & !G1_rega[1];
G1_rega[1]_p2_out = !Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & !Q2_dffs[1] & !G1_rega[1] & C1_inst8;
G1_rega[1]_p4_out = C1L5 & !Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & !Q2_dffs[1] & G1_rega[1] & !C1_inst8;
G1_rega[1]_or_out = G1_rega[1]_p1_out # G1_rega[1]_p2_out # G1_rega[1]_p4_out;
G1_rega[1]_reg_input = G1_rega[1]_or_out;
G1_rega[1] = TFFE(G1_rega[1]_reg_input, D1_inst2, , , );


--G1_rega[0] is series_para_store:inst19|rega[0] at LC253
G1_rega[0]_p1_out = !C1L5 & !Q2_dffs[1] & !Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G1_rega[0];
G1_rega[0]_p2_out = !Q2_dffs[1] & !Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G1_rega[0] & C1_inst8;
G1_rega[0]_p4_out = C1L5 & !Q2_dffs[1] & !Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & G1_rega[0] & !C1_inst8;
G1_rega[0]_or_out = G1_rega[0]_p1_out # G1_rega[0]_p2_out # G1_rega[0]_p4_out;
G1_rega[0]_reg_input = G1_rega[0]_or_out;
G1_rega[0] = TFFE(G1_rega[0]_reg_input, D1_inst2, , , );


--G1_rega[11] is series_para_store:inst19|rega[11] at LC255
G1_rega[11]_p1_out = !C1L5 & Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & Q2_dffs[1] & !G1_rega[11];
G1_rega[11]_p2_out = Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & Q2_dffs[1] & !G1_rega[11] & C1_inst8;
G1_rega[11]_p4_out = C1L5 & Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & Q2_dffs[1] & G1_rega[11] & !C1_inst8;
G1_rega[11]_or_out = G1_rega[11]_p1_out # G1_rega[11]_p2_out # G1_rega[11]_p4_out;
G1_rega[11]_reg_input = G1_rega[11]_or_out;
G1_rega[11] = TFFE(G1_rega[11]_reg_input, D1_inst2, , , );


--G3_rega[10] is series_para_store:inst23|rega[10] at LC75
G3_rega[10]_p1_out = !C1L5 & Q2_dffs[1] & Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G3_rega[10];
G3_rega[10]_p2_out = Q2_dffs[1] & Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G3_rega[10] & C1_inst4;
G3_rega[10]_p4_out = C1L5 & Q2_dffs[1] & Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & G3_rega[10] & !C1_inst4;
G3_rega[10]_or_out = G3_rega[10]_p1_out # G3_rega[10]_p2_out # G3_rega[10]_p4_out;
G3_rega[10]_reg_input = G3_rega[10]_or_out;
G3_rega[10] = TFFE(G3_rega[10]_reg_input, D1_inst2, , , );


--G3_rega[9] is series_para_store:inst23|rega[9] at LC55
G3_rega[9]_p1_out = !C1L5 & Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & !Q2_dffs[1] & !G3_rega[9];
G3_rega[9]_p2_out = Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & !Q2_dffs[1] & !G3_rega[9] & C1_inst4;
G3_rega[9]_p4_out = C1L5 & Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & !Q2_dffs[1] & G3_rega[9] & !C1_inst4;
G3_rega[9]_or_out = G3_rega[9]_p1_out # G3_rega[9]_p2_out # G3_rega[9]_p4_out;
G3_rega[9]_reg_input = G3_rega[9]_or_out;
G3_rega[9] = TFFE(G3_rega[9]_reg_input, D1_inst2, , , );


--G3_rega[8] is series_para_store:inst23|rega[8] at LC54
G3_rega[8]_p1_out = !C1L5 & !Q2_dffs[1] & Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G3_rega[8];
G3_rega[8]_p2_out = !Q2_dffs[1] & Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G3_rega[8] & C1_inst4;
G3_rega[8]_p4_out = C1L5 & !Q2_dffs[1] & Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & G3_rega[8] & !C1_inst4;
G3_rega[8]_or_out = G3_rega[8]_p1_out # G3_rega[8]_p2_out # G3_rega[8]_p4_out;
G3_rega[8]_reg_input = G3_rega[8]_or_out;
G3_rega[8] = TFFE(G3_rega[8]_reg_input, D1_inst2, , , );


--G3_rega[7] is series_para_store:inst23|rega[7] at LC56
G3_rega[7]_p1_out = !C1L5 & Q2_dffs[0] & Q2_dffs[1] & !Q2_dffs[3] & Q2_dffs[2] & !G3_rega[7];
G3_rega[7]_p2_out = Q2_dffs[0] & Q2_dffs[1] & !Q2_dffs[3] & Q2_dffs[2] & !G3_rega[7] & C1_inst4;
G3_rega[7]_p4_out = C1L5 & Q2_dffs[0] & Q2_dffs[1] & !Q2_dffs[3] & Q2_dffs[2] & G3_rega[7] & !C1_inst4;
G3_rega[7]_or_out = G3_rega[7]_p1_out # G3_rega[7]_p2_out # G3_rega[7]_p4_out;
G3_rega[7]_reg_input = G3_rega[7]_or_out;
G3_rega[7] = TFFE(G3_rega[7]_reg_input, D1_inst2, , , );


--G3_rega[6] is series_para_store:inst23|rega[6] at LC25
G3_rega[6]_p1_out = !C1L5 & Q2_dffs[1] & !Q2_dffs[0] & !Q2_dffs[3] & Q2_dffs[2] & !G3_rega[6];
G3_rega[6]_p2_out = Q2_dffs[1] & !Q2_dffs[0] & !Q2_dffs[3] & Q2_dffs[2] & !G3_rega[6] & C1_inst4;
G3_rega[6]_p4_out = C1L5 & Q2_dffs[1] & !Q2_dffs[0] & !Q2_dffs[3] & Q2_dffs[2] & G3_rega[6] & !C1_inst4;
G3_rega[6]_or_out = G3_rega[6]_p1_out # G3_rega[6]_p2_out # G3_rega[6]_p4_out;
G3_rega[6]_reg_input = G3_rega[6]_or_out;
G3_rega[6] = TFFE(G3_rega[6]_reg_input, D1_inst2, , , );


--G3_rega[5] is series_para_store:inst23|rega[5] at LC29
G3_rega[5]_p1_out = !C1L5 & Q2_dffs[0] & !Q2_dffs[1] & !Q2_dffs[3] & Q2_dffs[2] & !G3_rega[5];
G3_rega[5]_p2_out = Q2_dffs[0] & !Q2_dffs[1] & !Q2_dffs[3] & Q2_dffs[2] & !G3_rega[5] & C1_inst4;
G3_rega[5]_p4_out = C1L5 & Q2_dffs[0] & !Q2_dffs[1] & !Q2_dffs[3] & Q2_dffs[2] & G3_rega[5] & !C1_inst4;
G3_rega[5]_or_out = G3_rega[5]_p1_out # G3_rega[5]_p2_out # G3_rega[5]_p4_out;
G3_rega[5]_reg_input = G3_rega[5]_or_out;
G3_rega[5] = TFFE(G3_rega[5]_reg_input, D1_inst2, , , );


--G3_rega[4] is series_para_store:inst23|rega[4] at LC26
G3_rega[4]_p1_out = !C1L5 & !Q2_dffs[1] & !Q2_dffs[0] & !Q2_dffs[3] & Q2_dffs[2] & !G3_rega[4];
G3_rega[4]_p2_out = !Q2_dffs[1] & !Q2_dffs[0] & !Q2_dffs[3] & Q2_dffs[2] & !G3_rega[4] & C1_inst4;
G3_rega[4]_p4_out = C1L5 & !Q2_dffs[1] & !Q2_dffs[0] & !Q2_dffs[3] & Q2_dffs[2] & G3_rega[4] & !C1_inst4;
G3_rega[4]_or_out = G3_rega[4]_p1_out # G3_rega[4]_p2_out # G3_rega[4]_p4_out;
G3_rega[4]_reg_input = G3_rega[4]_or_out;
G3_rega[4] = TFFE(G3_rega[4]_reg_input, D1_inst2, , , );


--G3_rega[3] is series_para_store:inst23|rega[3] at LC242
G3_rega[3]_p1_out = !C1L5 & !Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & Q2_dffs[1] & !G3_rega[3];
G3_rega[3]_p2_out = !Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & Q2_dffs[1] & !G3_rega[3] & C1_inst4;
G3_rega[3]_p4_out = C1L5 & !Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & Q2_dffs[1] & G3_rega[3] & !C1_inst4;
G3_rega[3]_or_out = G3_rega[3]_p1_out # G3_rega[3]_p2_out # G3_rega[3]_p4_out;
G3_rega[3]_reg_input = G3_rega[3]_or_out;
G3_rega[3] = TFFE(G3_rega[3]_reg_input, D1_inst2, , , );


--G3_rega[2] is series_para_store:inst23|rega[2] at LC78
G3_rega[2]_p1_out = !C1L5 & Q2_dffs[1] & !Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G3_rega[2];
G3_rega[2]_p2_out = Q2_dffs[1] & !Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G3_rega[2] & C1_inst4;
G3_rega[2]_p4_out = C1L5 & Q2_dffs[1] & !Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & G3_rega[2] & !C1_inst4;
G3_rega[2]_or_out = G3_rega[2]_p1_out # G3_rega[2]_p2_out # G3_rega[2]_p4_out;
G3_rega[2]_reg_input = G3_rega[2]_or_out;
G3_rega[2] = TFFE(G3_rega[2]_reg_input, D1_inst2, , , );


--G3_rega[1] is series_para_store:inst23|rega[1] at LC79
G3_rega[1]_p1_out = !C1L5 & !Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & !Q2_dffs[1] & !G3_rega[1];
G3_rega[1]_p2_out = !Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & !Q2_dffs[1] & !G3_rega[1] & C1_inst4;
G3_rega[1]_p4_out = C1L5 & !Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & !Q2_dffs[1] & G3_rega[1] & !C1_inst4;
G3_rega[1]_or_out = G3_rega[1]_p1_out # G3_rega[1]_p2_out # G3_rega[1]_p4_out;
G3_rega[1]_reg_input = G3_rega[1]_or_out;
G3_rega[1] = TFFE(G3_rega[1]_reg_input, D1_inst2, , , );


--G3_rega[0] is series_para_store:inst23|rega[0] at LC65
G3_rega[0]_p1_out = !C1L5 & !Q2_dffs[1] & !Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G3_rega[0];
G3_rega[0]_p2_out = !Q2_dffs[1] & !Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & !G3_rega[0] & C1_inst4;
G3_rega[0]_p4_out = C1L5 & !Q2_dffs[1] & !Q2_dffs[3] & !Q2_dffs[2] & !Q2_dffs[0] & G3_rega[0] & !C1_inst4;
G3_rega[0]_or_out = G3_rega[0]_p1_out # G3_rega[0]_p2_out # G3_rega[0]_p4_out;
G3_rega[0]_reg_input = G3_rega[0]_or_out;
G3_rega[0] = TFFE(G3_rega[0]_reg_input, D1_inst2, , , );


--G3_rega[11] is series_para_store:inst23|rega[11] at LC66
G3_rega[11]_p1_out = !C1L5 & Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & Q2_dffs[1] & !G3_rega[11];
G3_rega[11]_p2_out = Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & Q2_dffs[1] & !G3_rega[11] & C1_inst4;
G3_rega[11]_p4_out = C1L5 & Q2_dffs[3] & !Q2_dffs[2] & Q2_dffs[0] & Q2_dffs[1] & G3_rega[11] & !C1_inst4;
G3_rega[11]_or_out = G3_rega[11]_p1_out # G3_rega[11]_p2_out # G3_rega[11]_p4_out;