dev3.v

来自「使用VHDL语言写的一些奇次和偶次分频源程序」· Verilog 代码 · 共 41 行

module	dev3(clk,clk_out);
input	clk;
output	clk_out;

reg		[1:0]counter1,counter2;
reg		reg1,reg2;
wire	clk_out;

always@(posedge clk)
begin
	if(counter1==2)
		begin
		counter1=0;
		reg1=~reg1;
		end
	else if(counter1==1)
		begin
		counter1=counter1+1'b1;
		reg1=~reg1;
		end
	else counter1=counter1+1'b1;
end

always@(negedge clk)
begin
	if(counter2==2)
		begin
		counter2=0;
		reg2=~reg2;
		end
	else if(counter2==1)
		begin
		counter2=counter2+1'b1;
		reg2=~reg2;
		end
	else counter2=counter2+1'b1;
end

assign	clk_out=reg1|reg2;

endmodule