偶数分频.txt

使用VHDL语言写的一些奇次和偶次分频源程序

module oufen(clk,rst,count,clk_odd);
  input        clk,rst;
  output       clk_odd;
  output[3:0]  count;
  reg          clk_odd;
  reg[3:0]     count;
  parameter    N = 8;
  
    always @ (posedge clk)
      if(! rst) 
        begin
          count <= 1'b0;
          clk_odd <= 1'b0;
        end
      else       
        if ( count < (N/2-1)) 
          begin          
            count <= count + 1'b1;            
          end
        else
          begin        
            count <= 1'b0;
            clk_odd <= ~clk_odd;      
          end
endmodule