upcnt6.vhd

来自「CF VHDL The CF+ design was designed usi」· VHDL 代码 · 共 67 行

-- File:			upcnt6.vhd

-- (c) Copyright 1999, 2003 Xilinx, Inc
-- All rights reserved

-- 
-- Author:		Jennifer Jenkins
--	     			Xilinx, Inc.
-- Purpose:		Up 6-bit counter
--
-- Created:		5-3-99 JLJ
-- Revised:		6-15-99 ALS
-- Modified:	2-5-2003 JRH
	


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;


entity upcnt6 is
	port(
			cnt_en       : in STD_LOGIC;                        -- Count enable
			clr          : in STD_LOGIC;                        -- Active low clear
			clk          : in STD_LOGIC;                        -- Clock
			qout         : inout STD_LOGIC_VECTOR (5 downto 0)
			);
		
end upcnt6;



architecture DEFINITION of upcnt6 is

constant RESET_ACTIVE : std_logic := '0';

signal q_int : UNSIGNED (5 downto 0);

begin

	process(clk, clr)
	begin
          
		-- Clear output register
		if (clr = RESET_ACTIVE) then
			q_int <= (others => '0');
	       
		-- On rising edge of clock count
		elsif (clk'event) and clk = '1' then

			-- If count enable is high
			if cnt_en = '1' then
				q_int <= q_int + 1;
			else
				q_int <= q_int;
			end if;
		end if;

	end process;

	qout <= STD_LOGIC_VECTOR(q_int);

end DEFINITION;