testbench.vhd

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		
		

		--------------------------------------------------------------
		-- ****** CF+ Write PRR register to clear CRdy_Bsy bit  ******
		--------------------------------------------------------------
		wait for 300 ns;
		reg_n <= '0';
		ce1_n <= '0';
		
		-- Write Pin Replacement Register (PRR)
		reg_n <= '0';
		ce1_n <= '0';
		host_addr <= BASE & PRR_ADDR;
		wait for 30 ns;
		we_n  <= '0';
		wait for 110 ns;
		host_data_low <= "00000010";		-- Mask Rdy_Bsy_n bit and clear CRdy_Bsy_n bit
		wait for 80 ns;
		we_n  <= '1';
		wait for 30 ns;
		host_data_low <= (others => 'Z');
		
		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');

		wait for 300 ns;
		reg_n <= '0';
		ce1_n <= '0';
		
		-- Write Pin Replacement Register (PRR)
		reg_n <= '0';
		ce1_n <= '0';
		host_addr <= BASE & PRR_ADDR;
		wait for 30 ns;
		we_n  <= '0';
		wait for 110 ns;
		host_data_low <= "00000000";		-- Remove Mask Rdy_Bsy_n bit
		wait for 80 ns;
		we_n  <= '1';
		wait for 30 ns;
		host_data_low <= (others => 'Z');

		-- Write Card Configuration and Staus Register (CSR)
		reg_n <= '0';
		ce1_n <= '0';
		host_addr <= BASE & CSR_ADDR;
		wait for 30 ns;
		we_n  <= '0';
		wait for 110 ns;
		host_data_low <= "00000000"; 	-- Disable stschg_n pin
		wait for 80 ns;
		we_n  <= '1';
		wait for 30 ns;
		host_data_low <= (others => 'Z');
		
		
		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');


		-----------------------------------------------------------------------------------
		-- ****** CF+ Write data to 9 locations in Common Memory (Intel StrataFlash) ******
		-----------------------------------------------------------------------------------
		wait for 300 ns;
		for i in 0 to 8 loop		-- write ten addresses
		
		-- Write the WRITE command
			host_addr <= TEST_ADDR_OUT(cycle_addr);
			wait for 30 ns;
			ce1_n <= '0';	-- 16-bit access
			ce2_n <= '0';	-- 16-bit access
			we_n <= '0';
			wait for 70 ns;
			host_data_low  <= WRITE_CMD;
			wait for 80 ns;
			we_n <= '1';
			wait for 30 ns;
			ce1_n <= '1';	-- 16-bit access
			ce2_n <= '1';	-- 16-bit access
			host_data_low  <= (others => 'Z');
			host_data_high <= (others => 'Z');
			
		-- Write the data to the memory location
			host_addr <= TEST_ADDR_OUT(cycle_addr);
			wait for 30 ns;
			ce1_n <= '0';	-- 16-bit access
			ce2_n <= '0';	-- 16-bit access
			we_n <= '0';
			wait for 70 ns;
			host_data_low  <= TEST_DATA_OUT_LOW(cycle_data_low);
			host_data_high <= TEST_DATA_OUT_HIGH(cycle_data_high);
			wait for 80 ns;
			we_n <= '1';
			cycle_data_high <= cycle_data_high + 1;
			wait for 30 ns;
			ce1_n <= '1';	-- 16-bit access
			ce2_n <= '1';	-- 16-bit access
			host_data_low  <= (others => 'Z');
			host_data_high <= (others => 'Z');
			wait for 300 us;
			
		-- Write the READ Status Register command
			host_addr <= TEST_ADDR_OUT(cycle_addr);
			wait for 30 ns;
			ce1_n <= '0';	-- 16-bit access
			ce2_n <= '0';	-- 16-bit access
			we_n <= '0';
			wait for 70 ns;
			host_data_low  <= READ_SRD;
			wait for 80 ns;
			we_n <= '1';
			wait for 30 ns;
			ce1_n <= '1';	-- 16-bit access
			ce2_n <= '1';	-- 16-bit access
			host_data_low  <= (others => 'Z');
			host_data_high <= (others => 'Z');
			
		-- Read the Status Register
			host_addr <= TEST_ADDR_OUT(cycle_addr);
			wait for 30 ns;
			ce1_n <= '0';	-- 16-bit access
			ce2_n <= '0';	-- 16-bit access
			oe_n <= '0';
			wait for 250 ns;
			oe_n <= '1';
			wait for 20 ns;
			ce1_n <= '1';
			ce2_n <= '1';
			cycle_addr <= cycle_addr + 1;
			cycle_data_low <= cycle_data_low + 1;
			wait for 30 ns;
		end loop;

		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');

		---------------------------------------------------------------------------
		-- ****** CF+ Write 8 bit data to Common Memory (Intel StrataFlash) ******
		---------------------------------------------------------------------------
		wait for 300 ns;
		--*******  Write Even byte on low data bus  **********
		-- Write the WRITE command
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 8-bit access low data bus
		we_n <= '0';
		wait for 70 ns;
		host_data_low  <= WRITE_CMD;
		wait for 80 ns;
		we_n <= '1';
		wait for 30 ns;
		ce1_n <= '1';	-- 8-bit access low data bus
		host_data_low  <= (others => 'Z');
		
		-- Write the data to the memory location
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 8-bit access low data bus
		we_n <= '0';
		wait for 70 ns;
		host_data_low  <= TEST_DATA_OUT_LOW(cycle_data_low);
		wait for 80 ns;
		we_n <= '1';
		wait for 30 ns;
		ce1_n <= '1';	-- 8-bit access low data bus
		host_data_low  <= (others => 'Z');
		wait for 300 us;
			
		-- Write the READ Status Register command
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 8-bit access low data bus
		we_n <= '0';
		wait for 70 ns;
		host_data_low  <= READ_SRD;
		wait for 80 ns;
		we_n <= '1';
		wait for 30 ns;
		ce1_n <= '1';	-- 8-bit access low data bus
		host_data_low  <= (others => 'Z');
			
		-- Read the Status Register
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 8-bit access low data bus
		oe_n <= '0';
		wait for 250 ns;
		oe_n <= '1';
		wait for 20 ns;
		ce1_n <= '1';
		cycle_addr <= cycle_addr + 1;
		cycle_data_low <= cycle_data_low + 1;
		wait for 30 ns;

		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');



		wait for 300 ns;
		--*******  Write Odd byte on low data bus  **********
		-- Write the WRITE command
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 8-bit access low data bus
		we_n <= '0';
		wait for 70 ns;
		host_data_low  <= WRITE_CMD;
		wait for 80 ns;
		we_n <= '1';
		wait for 30 ns;
		ce1_n <= '1';	-- 8-bit access low data bus
		host_data_low  <= (others => 'Z');
		
		-- Write the data to the memory location
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 8-bit access low data bus
		we_n <= '0';
		wait for 70 ns;
		host_data_low  <= TEST_DATA_OUT_LOW(cycle_data_low);
		wait for 80 ns;
		we_n <= '1';
		wait for 30 ns;
		ce1_n <= '1';	-- 8-bit access low data bus
		host_data_low  <= (others => 'Z');
		wait for 300 us;
			
		-- Write the READ Status Register command
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 8-bit access low data bus
		we_n <= '0';
		wait for 70 ns;
		host_data_low  <= READ_SRD;
		wait for 80 ns;
		we_n <= '1';
		wait for 30 ns;
		ce1_n <= '1';	-- 8-bit access low data bus
		host_data_low  <= (others => 'Z');
			
		-- Read the Status Register
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 8-bit access low data bus
		oe_n <= '0';
		wait for 250 ns;
		oe_n <= '1';
		wait for 20 ns;
		ce1_n <= '1';
		cycle_addr <= cycle_addr + 1;
		cycle_data_low <= cycle_data_low + 1;
		wait for 30 ns;

		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');


		wait for 300 ns;
		--*******  Write Odd byte on high data bus  **********
		-- Write the WRITE command
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 8-bit access low data bus (commands must always be on low data bus)
		we_n <= '0';
		wait for 70 ns;
		host_data_low  <= WRITE_CMD;
		wait for 80 ns;
		we_n <= '1';
		wait for 30 ns;
		ce1_n <= '1';	-- 8-bit access low data bus (commands must always be on low data bus)
		host_data_low <= (others => 'Z');
		
		-- Write the data to the memory location
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce2_n <= '0';	-- 8-bit access high data bus
		we_n <= '0';
		wait for 70 ns;
		host_data_high  <= TEST_DATA_OUT_HIGH(cycle_data_high);
		wait for 80 ns;
		we_n <= '1';
		wait for 30 ns;
		ce2_n <= '1';	-- 8-bit access high data bus
		host_data_high  <= (others => 'Z');
		wait for 300 us;
			
		-- Write the READ Status Register command
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 8-bit access low data bus (commands must always be on low data bus)
		we_n <= '0';
		wait for 70 ns;
		host_data_low  <= READ_SRD;
		wait for 80 ns;
		we_n <= '1';
		wait for 30 ns;
		ce1_n <= '1';	-- 8-bit access low data bus (commands must always be on low data bus)
		host_data_low  <= (others => 'Z');
			
		-- Read the Status Register
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 8-bit access low data bus (status register always on low data bus)
		oe_n <= '0';
		wait for 250 ns;
		oe_n <= '1';
		wait for 20 ns;
		ce1_n <= '1';	-- 8-bit access low data bus (status register always on low data bus)
		cycle_addr <= cycle_addr + 1;
		cycle_data_high <= cycle_data_high + 1;
		wait for 30 ns;

		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');


		

	
		wait;
		
	end process;



	cf_plus_top: cf_plus
	port map(	host_addr		=> host_addr,
					ce1_n				=> ce1_n,
					ce2_n				=> ce2_n,
					iord_n			=> iord_n,
					iowr_n			=> iowr_n,
					oe_n				=> oe_n,
					reg_n				=> reg_n,
					reset				=> reset,
					we_n				=> we_n,
					stschg_n			=> stschg_n,
					inpack_n			=> inpack_n,
					ireq_n			=> ireq_n,
					wait_n			=> wait_n,
					host_data_low	=> host_data_low,
					host_data_high	=> host_data_high,
					cm_sts			=> cm_sts,
					cm_wait			=> cm_wait,
					cm_byte_n		=> cm_byte_n,
					cm_addr			=> cm_addr,
					cm_reset			=> cm_reset,
					cm_read_n		=> cm_read_n,
					cm_data			=> cm_data,
					cm_ce_n			=> cm_ce0,
					cm_write_n		=> cm_write_n,
					dsp_clk			=> dsp_clk,
					dsp_addr			=> dsp_addr,
					dsp_ioms_n		=> dsp_ioms_n,
					dsp_rd_n			=> dsp_rd_n,
					dsp_wr_n			=> dsp_wr_n,
					dsp_data			=> dsp_data
					);

	flash_memory: StrataFlash3V
	port map(	A0   				=> cm_a_low,
					A    				=> cm_a_high,
					DQ   				=> cm_data,
					CEb  				=> cm_ce0,
					OEb  				=> cm_read_n,
					WEb  				=> cm_write_n,
					RPb  				=> cm_reset,
					BYTEb				=> cm_byte_n,
					RPb_a				=> RPb_a_x,
					VCC  				=> VCC_x,
					VCCQ  			=> VCCQ_x,
					VPEN  			=> VPEN_x,
					GND   			=> GND_x,
					VSSQ  			=> VSSQ_x,
					STS   			=> cm_sts_bit
					);

end behave;