testbench.vhd

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

		-----------------------------------------------------------------
		wait for 1000 ns;
		-- Write Configuration Option Register (COR)
		reg_n <= '0';
		ce1_n <= '0';
		host_addr <= BASE & COR_ADDR;
		wait for 30 ns;
		we_n  <= '0';
		wait for 110 ns;
		host_data_low <= "01000101";		-- no reset, level IRQ mode, enable IRQ routing, enable I/O space
		wait for 80 ns;
		we_n  <= '1';
		wait for 30 ns;
		
		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');

		--------------------------------------------
		-- ****** CF+ Write Data to I/O Space ******
		--------------------------------------------
		wait for 300 ns;
		host_addr <= CF_ADDR_REG;		-- access the Address Register
		wait for 65 ns;
		reg_n <= '0';
		ce1_n <= '0';		-- 8 bit access
		ce2_n <= '1';		-- 8 bit access
		wait for 5 ns;
		iowr_n <= '0';
		wait for 105 ns;
		host_data_low  <= TEST_DATA_OUT_LOW(cycle_data_low);
		wait for 60 ns;
		iowr_n <= '1';
		reg_n <= '1';
		cycle_data_low <= cycle_data_low + 1;
		wait for 20 ns;
		ce1_n <= '1';
		host_addr <= (others => '1');		
		wait for 10 ns;
		host_data_low  <= (others => 'Z');
		
		-- idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');

		---------------------------------------------
		-- ****** DSP Read Data from I/O Space ******
		---------------------------------------------
		wait for 300 ns;
		wait until dsp_clk'event and dsp_clk = '1';
		wait for 7 ns;
		dsp_addr <= DSP_ADDR_REG;
		dsp_ioms_n <= '0';
		wait for 0.125 ns;
		dsp_rd_n <= '0';
		wait for 40.75 ns;
		dsp_rd_n <= '1';
		wait for 0.125 ns;

		-- DSP idle state
		dsp_addr <= (others => 'Z');
		dsp_ioms_n <= '1';
		dsp_rd_n <= '1';
		dsp_wr_n <= '1';
		dsp_data <= (others => 'Z');


		--------------------------------------------------------------------------------------------
		--------------------------------------------------------------------------------------------
		-- ***** Test I/O Enable IRQ# Routing bit CONF2 disables irq_n signal on CF+ interface *****
		--------------------------------------------------------------------------------------------
		--------------------------------------------------------------------------------------------

		-------------------------------------------------------------
		-- ****** CF+ Write to the COR to disable IRQ# routing ******
		-------------------------------------------------------------
		wait for 1000 ns;
		-- Write Configuration Option Register (COR)
		reg_n <= '0';
		ce1_n <= '0';
		host_addr <= BASE & COR_ADDR;
		wait for 30 ns;
		we_n  <= '0';
		wait for 110 ns;
		host_data_low <= "01000001";		-- no reset, level IRQ mode, disable IRQ routing, enable I/O space
		wait for 80 ns;
		we_n  <= '1';
		wait for 30 ns;
		
		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');


		--------------------------------------------
		-- ****** DSP Write Data to I/O Space ******
		--------------------------------------------
		wait for 300 ns;
		wait until dsp_clk'event and dsp_clk = '1';
		wait for 7 ns;
		dsp_addr <= DSP_ADDR_REG;
		dsp_ioms_n <= '0';
		wait for 0.125 ns;
		dsp_wr_n <= '0';
		wait for 2 ns;
		dsp_data <= TEST_DSP_DATA_OUT(cycle_data_dsp);
		wait for 39.75 ns;
		cycle_data_dsp <= cycle_data_dsp + 1;
		dsp_wr_n <= '1';
		wait for 2.125 ns;

		-- DSP idle state
		dsp_addr <= (others => 'Z');
		dsp_ioms_n <= '1';
		dsp_rd_n <= '1';
		dsp_wr_n <= '1';
		dsp_data <= (others => 'Z');

		---------------------------------------------
		-- ****** CF+ Read Data from I/O Space ******
		---------------------------------------------
		-- *** Read data from Address Register to clear the Status Register bit 7 ***
		wait for 300 ns;
		host_addr <= CF_ADDR_REG;		-- access the Address Register
		wait for 15 ns;
		reg_n <= '0';
		ce1_n <= '0';		-- 8 bit access
		ce2_n <= '1';		-- 8 bit access
		wait for 5 ns;
		iord_n <= '0';
		wait for 165 ns;
		iord_n <= '1';
		reg_n <= '1';
		wait for 20 ns;
		ce1_n <= '1';
		
		-- idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		
		-------------------------------------------------------------
		-- ****** CF+ Write to the COR to enable IRQ# routing ******
		-------------------------------------------------------------
		wait for 1000 ns;
		-- Write Configuration Option Register (COR)
		reg_n <= '0';
		ce1_n <= '0';
		host_addr <= BASE & COR_ADDR;
		wait for 30 ns;
		we_n  <= '0';
		wait for 110 ns;
		host_data_low <= "01000101";		-- no reset, level IRQ mode, enable IRQ routing, enable I/O space
		wait for 80 ns;
		we_n  <= '1';
		wait for 30 ns;
		
		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');


		-- ********************************************************************************
		-- ****************************** Test Common Memory ******************************
		-- ********************************************************************************

		---------------------------------------------------------------------------------
		-- ****** CF+ Read initialized data from Common Memory (Intel StrataFlash) ******
		---------------------------------------------------------------------------------
		wait for 1000 ns;
		-- 16 bit access both odd & even bytes
		for i in 0 to 4 loop		-- read five addresses
			host_addr <= TEST_ADDR_OUT(cycle_addr);
			wait for 30 ns;
			ce1_n <= '0';	-- 16-bit access
			ce2_n <= '0';	-- 16-bit access
			oe_n <= '0';
			wait for 250 ns;
			oe_n <= '1';
			cycle_addr <= cycle_addr + 1;
			wait for 20 ns;
			ce1_n <= '1';
			ce2_n <= '1';
		end loop;

		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		
		wait for 300 ns;

		-- 16 bit access odd byte only
		for i in 0 to 4 loop		-- read five addresses
			host_addr <= TEST_ADDR_OUT(cycle_addr);
			wait for 30 ns;
			ce1_n <= '1';	-- 16-bit access
			ce2_n <= '0';	-- 16-bit access
			oe_n <= '0';
			wait for 250 ns;
			oe_n <= '1';
			cycle_addr <= cycle_addr + 1;
			wait for 20 ns;
			ce1_n <= '1';
			ce2_n <= '1';
		end loop;

		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		
		wait for 300 ns;

		-- 8 bit access odd byte only
		for i in 0 to 4 loop		-- read five addresses
			host_addr <= TEST_ADDR_OUT(cycle_addr);
			wait for 30 ns;
			ce1_n <= '0';	-- 16-bit access
			ce2_n <= '1';	-- 16-bit access
			oe_n <= '0';
			wait for 250 ns;
			oe_n <= '1';
			cycle_addr <= cycle_addr + 1;
			wait for 20 ns;
			ce1_n <= '1';
			ce2_n <= '1';
		end loop;

		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		
		wait for 300 ns;

		-- 8/16 bit access even byte only
		for i in 0 to 4 loop		-- read five addresses
			host_addr <= TEST_ADDR_OUT(cycle_addr);
			wait for 30 ns;
			ce1_n <= '0';	-- 16-bit access
			ce2_n <= '1';	-- 16-bit access
			oe_n <= '0';
			wait for 250 ns;
			oe_n <= '1';
			cycle_addr <= cycle_addr + 1;
			wait for 20 ns;
			ce1_n <= '1';
			ce2_n <= '1';
		end loop;

		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');



		------------------------------------------------------------------------------------
		-- ****** CF+ Write data to ONE location in Common Memory (Intel StrataFlash) ****** 
		-- ****** to test the changed bit, CRdy_Bsy_n bit, and MRdy_Bsy_n bit 			******
		------------------------------------------------------------------------------------
		wait for 300 ns;
		
		-- Write the WRITE command
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 16-bit access
		ce2_n <= '0';	-- 16-bit access
		we_n <= '0';
		wait for 70 ns;
		host_data_low  <= WRITE_CMD;
		wait for 80 ns;
		we_n <= '1';
		wait for 30 ns;
		ce1_n <= '1';	-- 16-bit access
		ce2_n <= '1';	-- 16-bit access
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
			
		-- Write the data to the memory location
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 16-bit access
		ce2_n <= '0';	-- 16-bit access
		we_n <= '0';
		wait for 70 ns;
		host_data_low  <= TEST_DATA_OUT_LOW(cycle_data_low);
		host_data_high <= TEST_DATA_OUT_HIGH(cycle_data_high);
		wait for 80 ns;
		we_n <= '1';
		cycle_data_high <= cycle_data_high + 1;
		wait for 30 ns;
		ce1_n <= '1';	-- 16-bit access
		ce2_n <= '1';	-- 16-bit access
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		wait for 300 us;
			
		-- Write the READ Status Register command
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 16-bit access
		ce2_n <= '0';	-- 16-bit access
		we_n <= '0';
		wait for 70 ns;
		host_data_low  <= READ_SRD;
		wait for 80 ns;
		we_n <= '1';
		wait for 30 ns;
		ce1_n <= '1';	-- 16-bit access
		ce2_n <= '1';	-- 16-bit access
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		
		-- Read the Status Register
		host_addr <= TEST_ADDR_OUT(cycle_addr);
		wait for 30 ns;
		ce1_n <= '0';	-- 16-bit access
		ce2_n <= '0';	-- 16-bit access
		oe_n <= '0';
		wait for 250 ns;
		oe_n <= '1';
		wait for 20 ns;
		ce1_n <= '1';
		ce2_n <= '1';
		cycle_addr <= cycle_addr + 1;
		cycle_data_low <= cycle_data_low + 1;
		wait for 30 ns;

		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		
		------------------------------------------------------------------------------------
		-- ****** CF+ Read CSR and PRR registers to verify Changed and CRdy_Bsy bits  ******
		------------------------------------------------------------------------------------
		wait for 300 ns;

		reg_n <= '0';
		ce1_n <= '0';
		
		-- Read Card Configuration and Staus Register (CSR)
		host_addr <= BASE & CSR_ADDR;
		wait for 30 ns;
		oe_n <= '0';
		wait for 250 ns;
		oe_n <= '1';
		wait for 20 ns;
		
		-- Read Pin Replacement Register (PRR)
		host_addr <= BASE & PRR_ADDR;
		wait for 30 ns;
		oe_n <= '0';
		wait for 250 ns;
		oe_n <= '1';
		wait for 20 ns;
		
		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';