testbench.vhd

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		
	
		--------------------------------------------------------------------------------------------
		--------------------------------------------------------------------------------------------
		-- ****** Check wait_n signal when DSP is reading at same time CF+ is trying to write ******
		--------------------------------------------------------------------------------------------
		--------------------------------------------------------------------------------------------
		-- DSP Read Data from I/O Space
		wait for 300 ns;
		wait until dsp_clk'event and dsp_clk = '1';
		wait for 7 ns;
		dsp_addr <= DSP_ADDR_REG;
		dsp_ioms_n <= '0';
		wait for 0.125 ns;
		dsp_rd_n <= '0';

		-- CF+ Tries to write
		host_addr <= CF_ADDR_REG;		-- access the Address Register
		wait for 65 ns;
		reg_n <= '0';
		ce1_n <= '0';		-- 8 bit access
		ce2_n <= '1';		-- 8 bit access
		wait for 5 ns;
		iowr_n <= '0';

		wait for 300.75 ns;	-- extended DSP write pulse
		dsp_rd_n <= '1';
		wait for 0.125 ns;

		-- DSP idle state
		dsp_addr <= (others => 'Z');
		dsp_ioms_n <= '1';
		dsp_rd_n <= '1';
		dsp_wr_n <= '1';
		dsp_data <= (others => 'Z');
		
		-- Finish CF+ write cycle
		wait for 105 ns;
		host_data_low  <= TEST_DATA_OUT_LOW(cycle_data_low);
		wait for 60 ns;
		iowr_n <= '1';
		reg_n <= '1';
		cycle_data_low <= cycle_data_low + 1;
		wait for 20 ns;
		ce1_n <= '1';
		host_addr <= (others => '1');		
		wait for 10 ns;

		-- idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');

		-----------------------------------------------------------------------------------------------------
		-----------------------------------------------------------------------------------------------------
		-- *** Check Status Register bit 6 prevents a DSP write unless the Address Register has been read ***
		-- *** The current state of the Status Register is bit 6 is HIGH indicating new data is ready     ***
		-- *** from the CF+ interface to be read by the DSP                                               ***
		-----------------------------------------------------------------------------------------------------
		-----------------------------------------------------------------------------------------------------
		--------------------------------------------
		-- ****** DSP Write Data to I/O Space ******
		--------------------------------------------
		wait for 300 ns;
		wait until dsp_clk'event and dsp_clk = '1';
		wait for 7 ns;
		dsp_addr <= DSP_ADDR_REG;
		dsp_ioms_n <= '0';
		wait for 0.125 ns;
		dsp_wr_n <= '0';
		wait for 2 ns;
		dsp_data <= TEST_DSP_DATA_OUT(cycle_data_dsp);
		wait for 39.75 ns;
		dsp_wr_n <= '1';
		wait for 2.125 ns;

		-- DSP idle state
		dsp_addr <= (others => 'Z');
		dsp_ioms_n <= '1';
		dsp_rd_n <= '1';
		dsp_wr_n <= '1';
		dsp_data <= (others => 'Z');
		
		---------------------------------------------
		-- ****** DSP Read Data from I/O Space ******
		---------------------------------------------
		-- *** Read data from Address Register to clear the Status Register bit 6 ***
		wait for 300 ns;
		wait until dsp_clk'event and dsp_clk = '1';
		wait for 7 ns;
		dsp_addr <= DSP_ADDR_REG;
		dsp_ioms_n <= '0';
		wait for 0.125 ns;
		dsp_rd_n <= '0';
		wait for 40.75 ns;
		dsp_rd_n <= '1';
		wait for 0.125 ns;

		-- DSP idle state
		dsp_addr <= (others => 'Z');
		dsp_ioms_n <= '1';
		dsp_rd_n <= '1';
		dsp_wr_n <= '1';
		dsp_data <= (others => 'Z');

		--------------------------------------------
		-- ****** DSP Write Data to I/O Space ******
		--------------------------------------------
		-- *** Write to Address Register to set bit 7 of the Status Register to set up for next test ***
		wait for 300 ns;
		wait until dsp_clk'event and dsp_clk = '1';
		wait for 7 ns;
		dsp_addr <= DSP_ADDR_REG;
		dsp_ioms_n <= '0';
		wait for 0.125 ns;
		dsp_wr_n <= '0';
		wait for 2 ns;
		dsp_data <= TEST_DSP_DATA_OUT(cycle_data_dsp);
		wait for 39.75 ns;
		cycle_data_dsp <= cycle_data_dsp + 1;
		dsp_wr_n <= '1';
		wait for 2.125 ns;

		-- DSP idle state
		dsp_addr <= (others => 'Z');
		dsp_ioms_n <= '1';
		dsp_rd_n <= '1';
		dsp_wr_n <= '1';
		dsp_data <= (others => 'Z');

		-----------------------------------------------------------------------------------------------------
		-----------------------------------------------------------------------------------------------------
		-- *** Check Status Register bit 7 prevents a CF+ write unless the Address Register has been read ***
		-- *** The current state of the Status Register is bit 7 is HIGH indicating new data is ready     ***
		-- *** from the DSP to be read by the CF+ interface                                               ***
		-----------------------------------------------------------------------------------------------------
		-----------------------------------------------------------------------------------------------------
		--------------------------------------------
		-- ****** CF+ Write Data to I/O Space ******
		--------------------------------------------
		wait for 300 ns;
		host_addr <= CF_ADDR_REG;		-- access the Address Register
		wait for 65 ns;
		reg_n <= '0';
		ce1_n <= '0';		-- 8 bit access
		ce2_n <= '1';		-- 8 bit access
		wait for 5 ns;
		iowr_n <= '0';
		wait for 105 ns;
		host_data_low  <= TEST_DATA_OUT_LOW(cycle_data_low);
		wait for 60 ns;
		iowr_n <= '1';
		reg_n <= '1';
		wait for 20 ns;
		ce1_n <= '1';
		host_addr <= (others => '1');		
		wait for 10 ns;
		host_data_low  <= (others => 'Z');
		
		-- idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		

		---------------------------------------------
		---------------------------------------------
		-- **** Test I/O space Status Register ****
		---------------------------------------------
		---------------------------------------------
		---------------------------------------------
		-- ****** CF+ Read Data from I/O Space ******
		---------------------------------------------
		-- *** Read data from Address Register to clear the Status Register bit 7 ***
		wait for 300 ns;
		host_addr <= CF_ADDR_REG;		-- access the Address Register
		wait for 15 ns;
		reg_n <= '0';
		ce1_n <= '0';		-- 8 bit access
		ce2_n <= '1';		-- 8 bit access
		wait for 5 ns;
		iord_n <= '0';
		wait for 165 ns;
		iord_n <= '1';
		reg_n <= '1';
		wait for 20 ns;
		ce1_n <= '1';
		
		-- idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		
		--------------------------------------------
		-- ****** CF+ Write Data to I/O Space ******
		--------------------------------------------
		-- *** Write to Address Register to test that bit 7 of Status Register has cleared ***
		wait for 300 ns;
		host_addr <= CF_ADDR_REG;		-- access the Address Register
		wait for 65 ns;
		reg_n <= '0';
		ce1_n <= '0';		-- 8 bit access
		ce2_n <= '1';		-- 8 bit access
		wait for 5 ns;
		iowr_n <= '0';
		wait for 105 ns;
		host_data_low  <= TEST_DATA_OUT_LOW(cycle_data_low);
		wait for 60 ns;
		iowr_n <= '1';
		reg_n <= '1';
		cycle_data_low <= cycle_data_low + 1;
		wait for 20 ns;
		ce1_n <= '1';
		host_addr <= (others => '1');		
		wait for 10 ns;
		host_data_low  <= (others => 'Z');
		
		-- idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');

		---------------------------------------------
		-- ****** DSP Read Data from I/O Space ******
		---------------------------------------------
		-- *** Read data from Address Register to clear the Status Register bit 6 ***
		wait for 300 ns;
		wait until dsp_clk'event and dsp_clk = '1';
		wait for 7 ns;
		dsp_addr <= DSP_ADDR_REG;
		dsp_ioms_n <= '0';
		wait for 0.125 ns;
		dsp_rd_n <= '0';
		wait for 40.75 ns;
		dsp_rd_n <= '1';
		wait for 0.125 ns;

		-- DSP idle state
		dsp_addr <= (others => 'Z');
		dsp_ioms_n <= '1';
		dsp_rd_n <= '1';
		dsp_wr_n <= '1';
		dsp_data <= (others => 'Z');


		------------------------------------------------------------
		------------------------------------------------------------
		-- ****** CF+ Write to the COR to test pulse mode IRQ ******
		------------------------------------------------------------
		------------------------------------------------------------
		wait for 1000 ns;
		-- Write Configuration Option Register (COR)
		reg_n <= '0';
		ce1_n <= '0';
		host_addr <= BASE & COR_ADDR;
		wait for 30 ns;
		we_n  <= '0';
		wait for 110 ns;
		host_data_low <= "00000101";		-- no reset, pulse IRQ mode, enable IRQ routing, enable I/O space
		wait for 80 ns;
		we_n  <= '1';
		wait for 30 ns;
		
		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');


		--------------------------------------------
		-- ****** DSP Write Data to I/O Space ******
		--------------------------------------------
		wait for 300 ns;
		wait until dsp_clk'event and dsp_clk = '1';
		wait for 7 ns;
		dsp_addr <= DSP_ADDR_REG;
		dsp_ioms_n <= '0';
		wait for 0.125 ns;
		dsp_wr_n <= '0';
		wait for 2 ns;
		dsp_data <= TEST_DSP_DATA_OUT(cycle_data_dsp);
		wait for 39.75 ns;
		cycle_data_dsp <= cycle_data_dsp + 1;
		dsp_wr_n <= '1';
		wait for 2.125 ns;

		-- DSP idle state
		dsp_addr <= (others => 'Z');
		dsp_ioms_n <= '1';
		dsp_rd_n <= '1';
		dsp_wr_n <= '1';
		dsp_data <= (others => 'Z');
		

		---------------------------------------------
		-- ****** CF+ Read Data from I/O Space ******
		---------------------------------------------
		wait for 1 us;
		host_addr <= CF_ADDR_REG;		-- access the Address Register
		wait for 15 ns;
		reg_n <= '0';
		ce1_n <= '0';		-- 8 bit access
		ce2_n <= '1';		-- 8 bit access
		wait for 5 ns;
		iord_n <= '0';
		wait for 165 ns;
		iord_n <= '1';
		reg_n <= '1';
		wait for 20 ns;
		ce1_n <= '1';
		
		-- idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		
		------------------------------------------------------------------
		------------------------------------------------------------------
		-- ****** CF+ Write to the COR to test I/O disable function ******
		------------------------------------------------------------------
		------------------------------------------------------------------
		wait for 1000 ns;
		-- Write Configuration Option Register (COR)
		reg_n <= '0';
		ce1_n <= '0';
		host_addr <= BASE & COR_ADDR;
		wait for 30 ns;
		we_n  <= '0';
		wait for 110 ns;
		host_data_low <= "01000100";		-- no reset, level IRQ mode, enable IRQ routing, disable I/O space
		wait for 80 ns;
		we_n  <= '1';
		wait for 30 ns;
		
		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');


		--------------------------------------------
		-- ****** CF+ Write Data to I/O Space ******
		--------------------------------------------
		wait for 300 ns;
		host_addr <= CF_ADDR_REG;		-- access the Address Register
		wait for 65 ns;
		reg_n <= '0';
		ce1_n <= '0';		-- 8 bit access
		ce2_n <= '1';		-- 8 bit access
		wait for 5 ns;
		iowr_n <= '0';
		wait for 105 ns;
		host_data_low  <= TEST_DATA_OUT_LOW(cycle_data_low);
		wait for 60 ns;
		iowr_n <= '1';
		reg_n <= '1';
		cycle_data_low <= cycle_data_low + 1;
		wait for 20 ns;
		ce1_n <= '1';
		host_addr <= (others => '1');		
		wait for 10 ns;
		host_data_low  <= (others => 'Z');
		
		-- idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');

		
		-----------------------------------------------------------------
		-----------------------------------------------------------------
		-- ****** CF+ Write to the COR to test I/O enable function ******
		-----------------------------------------------------------------