testbench.vhd

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

		we_n  <= '0';
		wait for 110 ns;
		host_data_low <= "00000000";		-- Soft reset CLEAR
		wait for 80 ns;
		we_n  <= '1';
		wait for 30 ns;
		
		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');


		-- **********************************************************************************
		-- ************************************ Test CIS ************************************
		-- **********************************************************************************
		
		-----------------------------------------
		-- ******* CF+ Verify CIS contents ******
		-----------------------------------------
		wait for 300 ns;
		-- Read CIS
		reg_n <= '0';
		ce1_n <= '0';
		for i in 0 to 46 loop
			host_addr <= TEST_ADDR_OUT(cycle_addr);
			wait for 30 ns;
			oe_n <= '0';
			wait for 250 ns;
			oe_n <= '1';
			cycle_addr <= cycle_addr + 1;
			wait for 20 ns;
		end loop;

		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		

		-- **********************************************************************************
		-- ************************ Test Attribute Memory  Read/Write ************************
		-- **********************************************************************************

		-----------------------------------------------------------------------------
		-----------------------------------------------------------------------------
		-- ****** CF+ Verify Configuration Registers contain zero (reset) data ******
		-----------------------------------------------------------------------------
		-----------------------------------------------------------------------------
		wait for 1000 ns;
		-- Read Configuration Option Register (COR)
		reg_n <= '0';
		ce1_n <= '0';
		host_addr <= BASE & COR_ADDR;
		wait for 30 ns;
		oe_n <= '0';
		wait for 250 ns;
		oe_n <= '1';
		wait for 20 ns;
		
		-- Read Card Configuration and Staus Register (CSR)
		host_addr <= BASE & CSR_ADDR;
		wait for 30 ns;
		oe_n <= '0';
		wait for 250 ns;
		oe_n <= '1';
		wait for 20 ns;
		
		-- Read Pin Replacement Register (PRR)
		host_addr <= BASE & PRR_ADDR;
		wait for 30 ns;
		oe_n <= '0';
		wait for 250 ns;
		oe_n <= '1';
		wait for 20 ns;
		
		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		


		----------------------------------------------------------------------------------------------
		-- ****** CF+ Write to the Configuration Registers final configuration for rest of test ******
		----------------------------------------------------------------------------------------------
		wait for 300 ns;
		-- Write Configuration Option Register (COR)
		reg_n <= '0';
		ce1_n <= '0';
		host_addr <= BASE & COR_ADDR;
		wait for 30 ns;
		we_n  <= '0';
		wait for 110 ns;
		host_data_low <= "01000101";		-- no reset, level IRQ mode, enable IRQ routing, enable I/O function
		wait for 80 ns;
		we_n  <= '1';
		wait for 30 ns;
		host_data_low <= (others => 'Z');
		
		-- Write Card Configuration and Staus Register (CSR)
		reg_n <= '0';
		ce1_n <= '0';
		host_addr <= BASE & CSR_ADDR;
		wait for 30 ns;
		we_n  <= '0';
		wait for 110 ns;
		host_data_low <= "01000000"; 	-- Enable stschg_n pin
		wait for 80 ns;
		we_n  <= '1';
		wait for 30 ns;
		host_data_low <= (others => 'Z');
		
		-- Write Pin Replacement Register (PRR)
		reg_n <= '0';
		ce1_n <= '0';
		host_addr <= BASE & PRR_ADDR;
		wait for 30 ns;
		we_n  <= '0';
		wait for 110 ns;
		host_data_low <= "00000000";		--No mask bit for Rdy_Bsy_n
		wait for 80 ns;
		we_n  <= '1';
		wait for 30 ns;
		host_data_low <= (others => 'Z');
		
		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');

		
		----------------------------------------------------------------------------
		----------------------------------------------------------------------------
		-- ****** CF+ Verify Configuration Registers contain the written data ******
		----------------------------------------------------------------------------
		----------------------------------------------------------------------------
		wait for 300 ns;
		-- Read Configuration Option Register (COR)
		reg_n <= '0';
		ce1_n <= '0';
		host_addr <= BASE & COR_ADDR;
		wait for 30 ns;
		oe_n <= '0';
		wait for 250 ns;
		oe_n <= '1';
		wait for 20 ns;
		
		-- Read Card Configuration and Staus Register (CSR)
		host_addr <= BASE & CSR_ADDR;
		wait for 30 ns;
		oe_n <= '0';
		wait for 250 ns;
		oe_n <= '1';
		wait for 20 ns;
		
		-- Read Pin Replacement Register (PRR)
		host_addr <= BASE & PRR_ADDR;
		wait for 30 ns;
		oe_n <= '0';
		wait for 250 ns;
		oe_n <= '1';
		wait for 20 ns;
		
		-- CF+ idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		

		-- ****************************************************************************
		-- ****************************** Test I/O Space ******************************
		-- ****************************************************************************

		--------------------------------------------
		-- ****** CF+ Write Data to I/O Space ******
		--------------------------------------------
		wait for 300 ns;
		host_addr <= CF_ADDR_REG;		-- access the Address Register
		wait for 65 ns;
		reg_n <= '0';
		ce1_n <= '0';		-- 8 bit access
		ce2_n <= '1';		-- 8 bit access
		wait for 5 ns;
		iowr_n <= '0';
		wait for 105 ns;
		host_data_low  <= TEST_DATA_OUT_LOW(cycle_data_low);
		wait for 60 ns;
		iowr_n <= '1';
		reg_n <= '1';
		cycle_data_low <= cycle_data_low + 1;
		wait for 20 ns;
		ce1_n <= '1';
		host_addr <= (others => '1');		
		wait for 10 ns;
		host_data_low  <= (others => 'Z');
		
		host_addr <= CF_DATA_REG;		-- access the I/O Data Register
		wait for 65 ns;
		reg_n <= '0';
		ce1_n <= '0';		-- 8 bit access
		ce2_n <= '1';		-- 8 bit access
		wait for 5 ns;
		iowr_n <= '0';
		wait for 105 ns;
		host_data_low  <= TEST_DATA_OUT_LOW(cycle_data_low);
		wait for 60 ns;
		iowr_n <= '1';
		reg_n <= '1';
		cycle_data_low <= cycle_data_low + 1;
		wait for 20 ns;
		ce1_n <= '1';
		host_addr <= (others => '1');		
		wait for 10 ns;
		host_data_low  <= (others => 'Z');

		-- idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		
		---------------------------------------------
		-- ****** DSP Read Data from I/O Space ******
		---------------------------------------------
		-- *** Check max spec for tcrd (per DSP Data Sheet) ***
		wait for 300 ns;
		wait until dsp_clk'event and dsp_clk = '1';
		wait for 7 ns;
		dsp_addr <= DSP_ADDR_REG;
		dsp_ioms_n <= '0';
		wait for 0.125 ns;
		dsp_rd_n <= '0';
		wait for 40.75 ns;
		dsp_rd_n <= '1';
		wait for 0.125 ns;

		-- DSP idle state
		dsp_addr <= (others => 'Z');
		dsp_ioms_n <= '1';
		dsp_rd_n <= '1';
		dsp_wr_n <= '1';
		dsp_data <= (others => 'Z');
		
		-- *** Check min spec for tcrd (per DSP Data Sheet) ***
		wait until dsp_clk'event and dsp_clk = '1';
		wait for 1 ns;
		dsp_addr <= DSP_DATA_REG;
		dsp_ioms_n <= '0';
		wait for 0.125 ns;
		dsp_rd_n <= '0';
		wait for 40.75 ns;
		dsp_rd_n <= '1';
		wait for 0.125 ns;

		-- DSP idle state
		dsp_addr <= (others => 'Z');
		dsp_ioms_n <= '1';
		dsp_rd_n <= '1';
		dsp_wr_n <= '1';
		dsp_data <= (others => 'Z');


		--------------------------------------------
		-- ****** DSP Write Data to I/O Space ******
		--------------------------------------------
		-- *** Check max spec for tcwr (per DSP Data Sheet) ***
		wait for 300 ns;
		wait until dsp_clk'event and dsp_clk = '1';
		wait for 7 ns;
		dsp_addr <= DSP_ADDR_REG;
		dsp_ioms_n <= '0';
		wait for 0.125 ns;
		dsp_wr_n <= '0';
		wait for 2 ns;
		dsp_data <= TEST_DSP_DATA_OUT(cycle_data_dsp);
		wait for 39.75 ns;
		cycle_data_dsp <= cycle_data_dsp + 1;
		dsp_wr_n <= '1';
		wait for 2.125 ns;

		-- DSP idle state
		dsp_addr <= (others => 'Z');
		dsp_ioms_n <= '1';
		dsp_rd_n <= '1';
		dsp_wr_n <= '1';
		dsp_data <= (others => 'Z');
		
		-- *** Check min spec for tcwr (per DSP Data Sheet) ***
		wait until dsp_clk'event and dsp_clk = '1';
		wait for 1 ns;
		dsp_addr <= DSP_DATA_REG;
		dsp_ioms_n <= '0';
		wait for 0.125 ns;
		dsp_wr_n <= '0';
		wait for 2 ns;
		dsp_data <= TEST_DSP_DATA_OUT(cycle_data_dsp);
		wait for 39.75 ns;
		cycle_data_dsp <= cycle_data_dsp + 1;
		dsp_wr_n <= '1';
		wait for 2.125 ns;

		-- DSP idle state
		dsp_addr <= (others => 'Z');
		dsp_ioms_n <= '1';
		dsp_rd_n <= '1';
		dsp_wr_n <= '1';
		dsp_data <= (others => 'Z');


		---------------------------------------------
		-- ****** CF+ Read Data from I/O Space ******
		---------------------------------------------
		wait for 300 ns;
		host_addr <= CF_ADDR_REG;		-- access the Address Register
		wait for 15 ns;
		reg_n <= '0';
		ce1_n <= '0';		-- 8 bit access
		ce2_n <= '1';		-- 8 bit access
		wait for 5 ns;
		iord_n <= '0';
		wait for 165 ns;
		iord_n <= '1';
		reg_n <= '1';
		wait for 20 ns;
		ce1_n <= '1';
		
		host_addr <= CF_DATA_REG;		-- access the Data Register
		wait for 15 ns;
		reg_n <= '0';
		ce1_n <= '0';		-- 8 bit access
		ce2_n <= '1';		-- 8 bit access
		wait for 5 ns;
		iord_n <= '0';
		wait for 165 ns;
		iord_n <= '1';
		reg_n <= '1';
		wait for 20 ns;

		-- idle state
		reg_n <= '1';
		ce1_n <= '1';
		ce2_n <= '1';
		oe_n  <= '1';
		we_n  <= '1';
		iord_n  <= '1';
		iowr_n  <= '1';
		host_addr <= (others => '1');		
		host_data_low  <= (others => 'Z');
		host_data_high <= (others => 'Z');
		


		-----------------------------------------------------------------------------------------
		-----------------------------------------------------------------------------------------
		-- ***** Check wait_n signal when DSP is writing at same time CF+ is trying to read *****
		-----------------------------------------------------------------------------------------
		-----------------------------------------------------------------------------------------
		-- DSP Write Data to I/O Space 
		wait for 300 ns;
		wait until dsp_clk'event and dsp_clk = '1';
		wait for 7 ns;
		dsp_addr <= DSP_ADDR_REG;
		dsp_ioms_n <= '0';
		wait for 0.125 ns;
		dsp_wr_n <= '0';
		wait for 2 ns;
		dsp_data <= TEST_DSP_DATA_OUT(cycle_data_dsp);
		
		-- CF+ Tries to read
		host_addr <= CF_ADDR_REG;		-- access the Address Register
		wait for 15 ns;
		reg_n <= '0';
		ce1_n <= '0';		-- 8 bit access
		ce2_n <= '1';		-- 8 bit access
		wait for 5 ns;
		iord_n <= '0';
		
		wait for 300.75 ns;	-- extended DSP write pulse
		cycle_data_dsp <= cycle_data_dsp + 1;
		dsp_wr_n <= '1';
		wait for 2.125 ns;

		-- DSP idle state
		dsp_addr <= (others => 'Z');
		dsp_ioms_n <= '1';
		dsp_rd_n <= '1';
		dsp_wr_n <= '1';
		dsp_data <= (others => 'Z');
		
		-- Finish CF+ read cycle
		wait for 165 ns;
		iord_n <= '1';
		reg_n <= '1';
		wait for 20 ns;
		ce1_n <= '1';

		-- idle state