📄 testbench.vhd
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--***********************************************************************************************
-- testbench.vhd
-- (c) Copyright 2003 Xilinx, Inc
-- All rights reserved
--
-- Created: 2/4/2003 JRH
--***********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture behave of testbench is
constant CLK_PERIOD : time := 12.5 nS; -- 80MHz
-- *** Compact Flash interface signals ***
signal host_addr : std_logic_vector(10 downto 0);
signal ce1_n : std_logic;
signal ce2_n : std_logic;
signal iord_n : std_logic;
signal iowr_n : std_logic;
signal oe_n : std_logic;
signal reg_n : std_logic;
signal reset : std_logic;
signal we_n : std_logic;
signal stschg_n : std_logic;
signal inpack_n : std_logic;
signal ireq_n : std_logic;
signal wait_n : std_logic;
signal host_data_low : std_logic_vector(7 downto 0); -- data bus low byte
signal host_data_high : std_logic_vector(7 downto 0); -- data bus high byte (16 bit data busses only)
-- *** Flash Memory Signals ***
signal cm_sts : std_logic;
signal cm_wait : std_logic;
signal cm_byte_n : std_logic; -- common memory 16-bit/8-bit select
signal cm_ce_n : std_logic; -- common memory chip enable
signal cm_addr : std_logic_vector(10 downto 0); -- common memory address bus
signal cm_write_n : std_logic; -- common memory we
signal cm_read_n : std_logic; -- common memory oe
signal cm_reset : std_logic; -- common memory reset
signal cm_data : std_logic_vector(15 downto 0); -- Common Memory byte
signal cm_a : std_logic_vector(21 downto 0);
signal cm_ce0 : std_logic;
signal cm_a_low : std_logic; -- common memory address bus high bit
signal cm_a_high : std_logic_vector(20 downto 0); -- common memory address bus high bits
signal cm_sts_bit : bit;
-- Intel StrataFlash voltage levels
signal RPb_a_x : REAL := 3.6;
signal VCC_x : REAL := 3.0;
signal VCCQ_x : REAL := 3.0;
signal VPEN_x : REAL := 3.0;
signal GND_x : REAL := 0.0;
signal VSSQ_x : REAL := 0.0;
-- *** I/O Signals ***
signal dsp_clk : std_logic; -- clkout of DSP
signal dsp_addr : std_logic_vector (10 downto 0);
signal dsp_ioms_n : std_logic; -- I/O Memory Select, active low
signal dsp_rd_n : std_logic; -- Read strobe, active low
signal dsp_wr_n : std_logic; -- Read strobe, active low
signal dsp_data : std_logic_vector(7 downto 0);
-- used for data and address arrays
signal cycle_addr : integer := 0; -- index into address array
signal cycle_data_low : integer := 0; -- index into data array for low byte
signal cycle_data_high : integer := 0; -- index into data array for high byte
signal cycle_data_dsp : integer := 0; -- index into data array with respect to DSP address
-- CF+ Configuration Register addresses
constant BASE : std_logic_vector(6 downto 0) := "0100000"; -- Configuration Registers Base Address (200h) (last 4 bits ommitted for adders)
constant COR_ADDR : std_logic_vector(3 downto 0) := "0000"; -- Configuration Option Register Address Adder (+0h)
constant CSR_ADDR : std_logic_vector(3 downto 0) := "0010"; -- Card Configuration and Staus Register Address Adder (+2h)
constant PRR_ADDR : std_logic_vector(3 downto 0) := "0100"; -- Pin Replacement Register Address Adder (+4h)
-- Intel StrataFlash commands
constant WRITE_CMD : std_logic_vector(7 downto 0) := "01000000"; -- 40\h
constant READ_CMD : std_logic_vector(7 downto 0) := "11111111"; -- FF\h
constant READ_SRD : std_logic_vector(7 downto 0) := "01110000"; -- 70\h
constant ERASE_CMD : std_logic_vector(7 downto 0) := "00100000"; -- 20\h
constant CONFIRM : std_logic_vector(7 downto 0) := "11010000"; -- D0\h
constant BLOCK_ERASE_ADDR : std_logic_vector(10 downto 0) := "00000000001";
-- I/O Space Register addresses
constant CF_ADDR_REG : std_logic_vector(10 downto 0) := "10000000000"; -- CF+ address for the Address Register (400h)
constant CF_DATA_REG : std_logic_vector(10 downto 0) := "10000000001"; -- CF+ address for the Data Register (401h)
constant DSP_ADDR_REG : std_logic_vector(10 downto 0) := "00000000001"; -- DSP address for the Address Register (001h)
constant DSP_DATA_REG : std_logic_vector(10 downto 0) := "00000000010"; -- DSP address for the Data Register (002h)
-- test data
type TEST_ADDR is array (0 to 79) of std_logic_vector (10 downto 0);
constant TEST_ADDR_OUT : TEST_ADDR := (
-- CIS access
-- Read CIS
"00000000000",
"00000000010",
"00000000100",
"00000000110",
"00000001000",
"00000001010",
"00000001100",
"00000001110",
"00000010000",
"00000010010",
"00000010100",
"00000010110",
"00000011000",
"00000011010",
"00000011100",
"00000011110",
"00000100000",
"00000100010",
"00000100100",
"00000100110",
"00000101000",
"00000101010",
"00000101100",
"00000101110",
"00000110000",
"00000110010",
"00000110100",
"00000110110",
"00000111000",
"00000111010",
"00000111100",
"00000111110",
"00001000000",
"00001000010",
"00001000100",
"00001000110",
"00001001000",
"00001001010",
"00001001100",
"00001001110",
"00001010000",
"00001010010",
"00001010100",
"00001010110",
"00001011000",
"00001011010",
"00001011100",
-- Common Memory access
-- Read initialized data from common memory at 10 addresses
-- 16 bit access both odd & even bytes
"00000000000",
"00000000010",
"00000000100",
"00000000110",
"00000001000",
-- 16 bit access odd byte only
"00000000000",
"00000000010",
"00000000100",
"00000000110",
"00000001000",
-- 8 bit access odd byte only
"00000000001",
"00000000011",
"00000000101",
"00000000111",
"00000001001",
-- 8/16 bit access even byte only
"00000000000",
"00000000010",
"00000000100",
"00000000110",
"00000001000",
-- Write 16 bit Data to common memory at 10 addresses
"00000000010",
"00000000100",
"00000000110",
"00000001000",
"00000001010",
"00000001100",
"00000001110",
"00000010000",
"00000010010",
"00000010100",
-- Write 8 bit Data to common memory
"00000010110",
"00000010111",
"00000011000"
);
type TEST_DATA_LOW is array (0 to 17) of std_logic_vector (7 downto 0);
constant TEST_DATA_OUT_LOW : TEST_DATA_LOW := (
-- CF+ Write data to Address Register
"11111010", -- FAh
-- CF+ Write data to Data Register
"11011110", -- DEh
-- CF+ Write data to Address Register
"11001110", -- CEh
-- CF+ Write data to Address Register
"11101101", -- EDh
"10111110", -- BEh
"10101101", -- ADh
-- Common Memory access
"10101101", -- ADh (DEAD)
"11011110", -- DEh (FADE)
"11101111", -- EFh (BEEF)
"10101111", -- AFh (DEAF)
"11101101", -- EDh (ACED)
"11001110", -- CEh (FACE)
"10101101", -- ADh (BEAD)
"11101101", -- EDh (FEED)
"10101101", -- ADh (DEAD)
"11011110", -- DEh (FADE)
"10111110", -- BEh
"11101111" -- EFh
);
type TEST_DATA_HIGH is array (0 to 10) of std_logic_vector (7 downto 0);
constant TEST_DATA_OUT_HIGH : TEST_DATA_HIGH := (
-- Common Memory access
"11011110", -- DEh (DEAD)
"11111010", -- FAh (FADE)
"10111110", -- BEh (BEEF)
"11011110", -- DEh (DEAF)
"10101100", -- ACh (ACED)
"11111010", -- FAh (FACE)
"10111110", -- BEh (BEAD)
"11111110", -- FEh (FEED)
"11011110", -- DEh (DEAD)
"11111010", -- FAh (FADE)
"10101100" -- ACEh
);
type TEST_DSP_DATA is array (0 to 6) of std_logic_vector (7 downto 0);
constant TEST_DSP_DATA_OUT : TEST_DSP_DATA := (
"10111110", -- BEh
"11101111", -- EFh
"11011110", -- DEh
"10101100", -- ACh
"10111110", -- BEh
"11101111", -- EFh
"10111110" -- BEh
);
component cf_plus
port (
-- **** CF+ bus signals ****
-- inputs
host_addr : in std_logic_vector(10 downto 0); -- address bus
ce1_n : in std_logic;
ce2_n : in std_logic;
iord_n : in std_logic;
iowr_n : in std_logic;
oe_n : in std_logic;
reg_n : in std_logic;
reset : in std_logic;
we_n : in std_logic;
-- outputs
stschg_n : out std_logic;
inpack_n : out std_logic;
ireq_n : out std_logic; -- rdy_bsy_n for Memory Mode
wait_n : out std_logic;
-- inouts
host_data_low : inout std_logic_vector(7 downto 0); -- data bus low byte
host_data_high : inout std_logic_vector(7 downto 0); -- data bus high byte (16 bit data busses only)
-- **** 28F320J3a Intel StrataFlash Interface ****
-- inputs
cm_sts : in std_logic; -- common memory status
cm_wait : in std_logic; -- common memory status
-- outputs
cm_byte_n : out std_logic; -- common memory 16-bit/8-bit select
cm_addr : out std_logic_vector(10 downto 0); -- common memory address bus
cm_reset : out std_logic; -- common memory reset
-- inouts
cm_read_n : inout std_logic; -- common memory oe
cm_data : inout std_logic_vector(15 downto 0); -- Common Memory word
cm_ce_n : inout std_logic; -- common memory chip enable
cm_write_n : inout std_logic; -- common memory we
-- **** ADSP-281xN I/O space interface ****
-- inputs
dsp_clk : in std_logic; -- clkout of DSP
dsp_addr : in std_logic_vector (10 downto 0);
dsp_ioms_n : in std_logic; -- I/O Memory Select, active low
dsp_rd_n : in std_logic; -- Read strobe, active low
dsp_wr_n : in std_logic; -- Read strobe, active low
-- inouts
dsp_data : inout std_logic_vector (7 downto 0)
);
end component;
component StrataFlash3V
port( A0 : in std_logic;
A : in std_logic_vector(21 downto 1);
DQ : inout std_logic_vector(15 downto 0);
CEb : in std_logic;
OEb : in std_logic;
WEb : in std_logic;
RPb : in std_logic;
BYTEb : in std_logic;
RPb_a : in real;
VCC : in real;
VCCQ : in real;
VPEN : in real;
GND : in real;
VSSQ : in real;
STS : out Bit
);
end component;
begin
-- ******************************************************************************************
-- ******************************* Common Memory Interconnect *******************************
-- ******************************************************************************************
cm_a <= "00000000000" & cm_addr;
-- split address signals
cm_a_low <= cm_a(0);
cm_a_high <= cm_a(21 downto 1);
cm_sts <= '0' when cm_sts_bit = '0' else '1';
cm_wait <= '1'; -- Intel Strataflash Memory does not have a wait type signal to extend
-- the bus cycle. Hold this pin High externally to the CPLD or remove
-- the logic from the cf_plus_control.vhd file.
-- ******************************************************************************************
-- ************************************ Clock Process ***************************************
-- ******************************************************************************************
create_clock: process
begin
dsp_clk <= '0';
wait for CLK_PERIOD/2;
dsp_clk <= '1';
wait for CLK_PERIOD/2;
end process;
-- ******************************************************************************************
-- *********************************** Main Control Process *********************************
-- ******************************************************************************************
main : process
variable i : integer := 0;
begin
-- DSP idle state
dsp_addr <= (others => 'Z');
dsp_ioms_n <= '1';
dsp_rd_n <= '1';
dsp_wr_n <= '1';
dsp_data <= (others => 'Z');
-- CF+ idle state
reg_n <= '1';
ce1_n <= '1';
ce2_n <= '1';
oe_n <= '1';
we_n <= '1';
iord_n <= '1';
iowr_n <= '1';
host_data_low <= (others => 'Z');
host_data_high <= (others => 'Z');
host_addr <= (others => 'Z');
-----------------------------------------
-- ********* CF+ Reset the card *********
-----------------------------------------
reset <= '0';
wait for 200 ns;
reset <= '1';
wait for 1 us;
reset <= '0';
-- **********************************************************************************
-- ************************************ Test COR ************************************
-- **********************************************************************************
-----------------------------------------
-- ******* Test SRESET bit in COR *******
-----------------------------------------
wait for 300 ns;
-- Write Configuration Option Register (COR)
reg_n <= '0';
ce1_n <= '0';
host_addr <= BASE & COR_ADDR;
wait for 30 ns;
we_n <= '0';
wait for 110 ns;
host_data_low <= "10000000"; -- Soft reset SET
wait for 80 ns;
we_n <= '1';
wait for 30 ns;
-- CF+ idle state
reg_n <= '1';
ce1_n <= '1';
ce2_n <= '1';
oe_n <= '1';
we_n <= '1';
iord_n <= '1';
iowr_n <= '1';
host_addr <= (others => '1');
host_data_low <= (others => 'Z');
host_data_high <= (others => 'Z');
-- Write Configuration Option Register (COR)
wait for 1 us;
reg_n <= '0';
ce1_n <= '0';
host_addr <= BASE & COR_ADDR;
wait for 30 ns;
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