cf_plus.npl

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

JDF F
// Created by Project Navigator ver 1.0
PROJECT cf_plus
DESIGN cf_plus Normal
DEVFAM xbr
DEVFAMTIME 0
DEVICE xc2c256
DEVICETIME 0
DEVPKG TQ144
DEVPKGTIME 1047672603
DEVSPEED -7
DEVSPEEDTIME 1047672603
FLOW XST VHDL
FLOWTIME 0
MODULE cf_plus_control.vhd
MODSTYLE cf_plus_control Normal
MODULE upcnt6.vhd
MODSTYLE upcnt6 Normal
MODULE dsp_interface.vhd
MODSTYLE dsp_interface Normal
MODULE cf_plus.vhd
MODSTYLE cf_plus Normal
MODULE cis.vhd
MODSTYLE cis Normal
MODULE attribute_memory.vhd
MODSTYLE attribute_memory Normal
DEPASSOC cf_plus cf_plus.ucf Normal
[Normal]
p_fitGenSimModel=xstvhd, xbr, Implementation.t_vm6File, 1047672729, True
p_PostParSimModelName=xstvhd, xbr, VHDL.t_postFitSimModel, 1047672729, timesim.vhd
p_SimModelTarget=xstvhd, xbr, VHDL.t_postFitSimModel, 1047672729, Modelsim_VHDL
xcpldFitDesTriMode=xstvhd, xbr, Implementation.t_vm6File, 1047672729, Float
xcpldFitDesUnused=xstvhd, xbr, Implementation.t_vm6File, 1051804858, Pullup
xcpldFitDesVolt=xstvhd, xbr, Implementation.t_vm6File, 1047672729, LVCMOS33
[STATUS-ALL]
cf_plus.ngcFile=WARNINGS,1056728854
cf_plus.vm6File=WARNINGS,1056728854
[STRATEGY-LIST]
Normal=True