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📄 cf_plus.rpt

📁 CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re
💻 RPT
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字号:
                  .....X..XXXXXXXXXXX..................... 12      12
cm_addr<2>        ......X....X............................ 2       2
io_interface_logic_io_status_en 
                  XX...X..XXXXXXXXXXX..XXXX............... 18      18
io_interface_logic_io_data_en 
                  XX...X..XXXXXXXXXXX.X.XXX............... 18      18
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
*********************************** FB6 ***********************************
This function block is part of I/O Bank number:               1
Number of signals used by logic mapping into function block:  30
Number of function block inputs used/remaining:               30/10
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   41/15
Signal                            Total   Loc     Pin   Pin      Pin   
Name                              Pt               #    Type     Use   
dsp_data<0>                       5       FB6_1   34    I/O      I/O   
dsp_data<1>                       5       FB6_2   35    CDR/I/O  I/O   
io_interface_logic_io_data_r<4>   3       FB6_3         (b)      (b)   
dsp_data<6>                       5       FB6_4   38    GCK/I/O  I/O   
io_interface_logic_io_data_r<3>   3       FB6_5         (b)      (b)   
io_interface_logic_io_data_r<2>   3       FB6_6         (b)      (b)   
io_interface_logic_io_data_r<7>   4       FB6_7         (b)      (b)   
io_interface_logic_io_data_r<6>   4       FB6_8         (b)      (b)   
io_interface_logic_io_data_r<1>   4       FB6_9         (b)      (b)   
io_interface_logic_io_data_r<0>   4       FB6_10        (b)      (b)   
io_interface_logic__n0185         2       FB6_11        (b)      (b)   
dsp_data<7>                       5       FB6_12  39    DGE/I/O  I/O   
dsp_data<2>                       4       FB6_13  40    I/O      I/O   
bvd2                              0       FB6_14  41    I/O      O     
csel                              0       FB6_15  42    I/O      O     
iois16_n                          0       FB6_16  43    I/O      O     

Signals Used by Logic in Function Block
  1: dsp_ioms_n        11: io_interface_logic_io_addr_reg<3> 
                                             21: io_interface_logic_io_data_reg<6> 
  2: io_interface_logic__n0183 
                       12: io_interface_logic_io_addr_reg<4> 
                                             22: io_interface_logic_io_data_reg<7> 
  3: io_interface_logic__n0185 
                       13: io_interface_logic_io_addr_reg<6> 
                                             23: io_interface_logic_io_status_en 
  4: io_interface_logic_dsp_addr_en 
                       14: io_interface_logic_io_addr_reg<7> 
                                             24: io_interface_logic_io_status_reg<0> 
  5: io_interface_logic_dsp_data_en 
                       15: io_interface_logic_io_data_en 
                                             25: io_interface_logic_io_status_reg<1> 
  6: io_interface_logic_dsp_status_en 
                       16: io_interface_logic_io_data_reg<0> 
                                             26: io_interface_logic_io_status_reg<6> 
  7: io_interface_logic_io_addr_en 
                       17: io_interface_logic_io_data_reg<1> 
                                             27: io_interface_logic_io_status_reg<7> 
  8: io_interface_logic_io_addr_reg<0> 
                       18: io_interface_logic_io_data_reg<2> 
                                             28: io_interface_logic_prs_state_ffd1 
  9: io_interface_logic_io_addr_reg<1> 
                       19: io_interface_logic_io_data_reg<3> 
                                             29: io_interface_logic_prs_state_ffd2 
 10: io_interface_logic_io_addr_reg<2> 
                       20: io_interface_logic_io_data_reg<4> 
                                             30: io_interface_logic_prs_state_ffd3 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
dsp_data<0>       X.XXXX.X.......X.......X...XXX.......... 11      11
dsp_data<1>       X.XXXX..X.......X.......X..XXX.......... 11      11
io_interface_logic_io_data_r<4> 
                  .X....X....X..X....X.......XXX.......... 8       8
dsp_data<6>       X.XXXX......X.......X....X.XXX.......... 11      11
io_interface_logic_io_data_r<3> 
                  .X....X...X...X...X........XXX.......... 8       8
io_interface_logic_io_data_r<2> 
                  .X....X..X....X..X.........XXX.......... 8       8
io_interface_logic_io_data_r<7> 
                  .X....X......XX......XX...XXXX.......... 10      10
io_interface_logic_io_data_r<6> 
                  .X....X.....X.X.....X.X..X.XXX.......... 10      10
io_interface_logic_io_data_r<1> 
                  .X....X.X.....X.X.....X.X..XXX.......... 10      10
io_interface_logic_io_data_r<0> 
                  .X....XX......XX......XX...XXX.......... 10      10
io_interface_logic__n0185 
                  ...XXX.....................XXX.......... 6       6
dsp_data<7>       X.XXXX.......X.......X....XXXX.......... 11      11
dsp_data<2>       X.XXX....X.......X.........XXX.......... 9       9
bvd2              ........................................ 0       0
csel              ........................................ 0       0
iois16_n          ........................................ 0       0
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
*********************************** FB7 ***********************************
This function block is part of I/O Bank number:               1
Number of signals used by logic mapping into function block:  12
Number of function block inputs used/remaining:               12/28
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   19/37
Signal                            Total   Loc     Pin   Pin      Pin   
Name                              Pt               #    Type     Use   
io_interface_logic_irq_count<2>   2       FB7_1         (b)      (b)   
io_interface_logic_irq_count<3>   2       FB7_2         (b)      (b)   
io_interface_logic_irq_count<4>   2       FB7_3         (b)      (b)   
io_interface_logic__n0187         2       FB7_4         (b)      (b)   
vcc1                              0       FB7_5   26    I/O      O     
vcc2                              0       FB7_6   25    I/O      O     
io_interface_logic_irq_count_en   5       FB7_7         (b)      (b)   
io_interface_logic_io_irq_n       5       FB7_8         (b)      (b)   
io_interface_logic_irq_count_clr  2       FB7_9         (b)      (b)   
io_interface_logic_io_write_n_sync
                                  2       FB7_10        (b)      (b)   
vs2                               0       FB7_11  24    I/O      O     
cd1                               0       FB7_12  23    I/O      O     
cd2                               0       FB7_13  22    I/O      O     
gnd1                              0       FB7_14  21    I/O      O     
gnd2                              0       FB7_15  20    I/O      O     
io_interface_logic_irq_count<1>   2       FB7_16  19    I/O      I     

Signals Used by Logic in Function Block
  1: N_PZ_566           5: io_interface_logic_irq_count<0> 
                                              9: io_interface_logic_irq_count<4> 
  2: cf_plus_logic_io_write_n 
                        6: io_interface_logic_irq_count<1> 
                                             10: io_interface_logic_irq_count_clr 
  3: io_interface_logic__n0187 
                        7: io_interface_logic_irq_count<2> 
                                             11: io_interface_logic_irq_count_en 
  4: io_interface_logic_io_status_reg<7> 
                        8: io_interface_logic_irq_count<3> 
                                             12: level_pulse_n 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
io_interface_logic_irq_count<2> 
                  ....XX...XX............................. 4       4
io_interface_logic_irq_count<3> 
                  ....XXX..XX............................. 5       5
io_interface_logic_irq_count<4> 
                  ....XXXX.XX............................. 6       6
io_interface_logic__n0187 
                  ....XXXXXXX............................. 7       7
vcc1              ........................................ 0       0
vcc2              ........................................ 0       0
io_interface_logic_irq_count_en 
                  X.XXXXXXX.XX............................ 10      10
io_interface_logic_io_irq_n 
                  X.XXXXXXX..X............................ 9       9
io_interface_logic_irq_count_clr 
                  X..X.......X............................ 3       3
io_interface_logic_io_write_n_sync 
                  XX...................................... 2       2
vs2               ........................................ 0       0
cd1               ........................................ 0       0
cd2               ........................................ 0       0
gnd1              ........................................ 0       0
gnd2              ........................................ 0       0
io_interface_logic_irq_count<1> 
                  ....X....XX............................. 3       3
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
*********************************** FB8 ***********************************
This function block is part of I/O Bank number:            

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