cf_plus.rpt

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

                  XX.X..X..XX..X...XX.X..X........XXXXXX.. 17      17
io_interface_logic_io_addr_reg<4> 
                  XX.X.X...XX.X....XX.X.X.........XXXXXX.. 17      17
io_interface_logic_io_addr_reg<3> 
                  XX.XX....XXX.....XX.XX..........XXXXXX.. 17      17
io_interface_logic_io_data_reg<5> 
                  X.XX..X..XX..X...XXXX.....X..X..XXXXXX.. 19      19
io_interface_logic_io_data_reg<4> 
                  X.XX.X...XX.X....XXXX.....X.X...XXXXXX.. 19      19
io_interface_logic_dsp_data_done 
                  X........X.......XXX............X.XXX... 9       9
io_interface_logic_io_data_reg<3> 
                  X.XXX....XXX.....XXXX.....XX....XXXXXX.. 19      19
N_PZ_703          .........X.......XX.X...........XXXXXX.. 10      10
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
*********************************** FB4 ***********************************
This function block is part of I/O Bank number:               2
Number of signals used by logic mapping into function block:  38
Number of function block inputs used/remaining:               38/2
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   53/3
Signal                            Total   Loc     Pin   Pin      Pin   
Name                              Pt               #    Type     Use   
inpack_n                          2       FB4_1   11    I/O      O     
(unused)                          0       FB4_2   12    I/O      I     
io_interface_logic_io_addr_en     3       FB4_3   13    I/O      I     
io_interface_logic_io_address_match
                                  4       FB4_4   14    I/O      I     
cf_plus_logic_attribute_memory_array/_n0007<6>12
                                  13      FB4_5   15    I/O      I     
cf_plus_logic_io_ireq_route       3       FB4_6   16    I/O      I     
cf_plus_logic_attribute_memory_array/host_crdy_bsy_n
                                  3       FB4_7         (b)      (b)   
cf_plus_logic_attribute_memory_array/conf<5>
                                  3       FB4_8         (b)      (b)   
cf_plus_logic_attribute_memory_array/conf<4>
                                  3       FB4_9         (b)      (b)   
cf_plus_logic_attribute_memory_array/conf<3>
                                  3       FB4_10        (b)      (b)   
cf_plus_logic_attribute_memory_array/mrdy_bsy_n
                                  3       FB4_11        (b)      (b)   
level_pulse_n                     3       FB4_12  17    I/O      I     
cf_plus_logic_attribute_memory_array/conf<1>
                                  3       FB4_13        (b)      (b)   
cf_plus_logic_attribute_memory_array/sigchg
                                  3       FB4_14  18    I/O      I     
cf_plus_logic_soft_reset          2       FB4_15        (b)      (b)   
cf_plus_logic_io_enab             3       FB4_16        (b)      (b)   

Signals Used by Logic in Function Block
  1: N_PZ_566          14: cf_plus_logic_soft_reset 
                                             27: host_data_low<1>.PIN 
  2: N_PZ_783          15: host_addr<0>      28: host_data_low<2>.PIN 
  3: cf_plus_logic_am_write_n 
                       16: host_addr<10>     29: host_data_low<3>.PIN 
  4: cf_plus_logic_attribute_memory_array/conf<1> 
                       17: host_addr<1>      30: host_data_low<4>.PIN 
  5: cf_plus_logic_attribute_memory_array/conf<3> 
                       18: host_addr<2>      31: host_data_low<5>.PIN 
  6: cf_plus_logic_attribute_memory_array/conf<4> 
                       19: host_addr<3>      32: host_data_low<6>.PIN 
  7: cf_plus_logic_attribute_memory_array/conf<5> 
                       20: host_addr<4>      33: host_data_low<7>.PIN 
  8: cf_plus_logic_attribute_memory_array/host_crdy_bsy_n 
                       21: host_addr<5>      34: io_interface_logic_io_addr_en 
  9: cf_plus_logic_attribute_memory_array/mrdy_bsy_n 
                       22: host_addr<6>      35: io_interface_logic_prs_state_ffd1 
 10: cf_plus_logic_attribute_memory_array/sigchg 
                       23: host_addr<7>      36: io_interface_logic_prs_state_ffd2 
 11: cf_plus_logic_io_enab 
                       24: host_addr<8>      37: io_interface_logic_prs_state_ffd3 
 12: cf_plus_logic_io_ireq_route 
                       25: host_addr<9>      38: level_pulse_n 
 13: cf_plus_logic_io_read_n 
                       26: host_data_low<0>.PIN 
                                            

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
inpack_n          ..........X.X.XXXXXXXXXXX............... 13      13
io_interface_logic_io_addr_en 
                  XX........X...XXXXXXXXXXX........XXXX... 18      18
io_interface_logic_io_address_match 
                  XX........X...XXXXXXXXXXX.........XXX... 17      17
cf_plus_logic_attribute_memory_array/_n0007<6>12 
                  .........X....XXXXXXXXXXX............X.. 13      13
cf_plus_logic_io_ireq_route 
                  ..X........X..XXXXXXXXXXX..X....X....... 15      15
cf_plus_logic_attribute_memory_array/host_crdy_bsy_n 
                  ..X....X......XXXXXXXXXXX.....X.X....... 15      15
cf_plus_logic_attribute_memory_array/conf<5> 
                  ..X...X.......XXXXXXXXXXX.....X.X....... 15      15
cf_plus_logic_attribute_memory_array/conf<4> 
                  ..X..X........XXXXXXXXXXX....X..X....... 15      15
cf_plus_logic_attribute_memory_array/conf<3> 
                  ..X.X.........XXXXXXXXXXX...X...X....... 15      15
cf_plus_logic_attribute_memory_array/mrdy_bsy_n 
                  ..X.....X.....XXXXXXXXXXX.X.....X....... 15      15
level_pulse_n     ..X...........XXXXXXXXXXX......XX....X.. 15      15
cf_plus_logic_attribute_memory_array/conf<1> 
                  ..XX..........XXXXXXXXXXX.X.....X....... 15      15
cf_plus_logic_attribute_memory_array/sigchg 
                  ..X......X....XXXXXXXXXXX......XX....... 15      15
cf_plus_logic_soft_reset 
                  ..X..........XXXXXXXXXXXX.......X....... 14      14
cf_plus_logic_io_enab 
                  ..X.......X...XXXXXXXXXXXX......X....... 15      15
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
*********************************** FB5 ***********************************
This function block is part of I/O Bank number:               1
Number of signals used by logic mapping into function block:  25
Number of function block inputs used/remaining:               25/15
Number of function block control terms used/remaining:        2/2
Number of PLA product terms used/remaining:                   56/0
Signal                            Total   Loc     Pin   Pin      Pin   
Name                              Pt               #    Type     Use   
(unused)                          0       FB5_1         (b)            
cm_addr<10>                       2       FB5_2   33    I/O      O     
(unused)                          0       FB5_3         (b)            
(unused)                          0       FB5_4   32    GCK/I/O  GCK   
cm_addr<1>                        2       FB5_5   31    I/O      O     
(unused)                          0       FB5_6   30    GCK/I/O  GCK/I 
(unused)                          0       FB5_7         (b)            
(unused)                          0       FB5_8         (b)            
io_interface_logic__n0183         2       FB5_9         (b)      (b)   
cf_plus_logic_attribute_memory_array/_n0007<4>11
                                  16      FB5_10        (b)      (b)   
cf_plus_logic_attribute_memory_array/_n0007<5>17
                                  10      FB5_11        (b)      (b)   
cf_plus_logic_attribute_memory_array/_n0007<7>15
                                  12      FB5_12        (b)      (b)   
cf_plus_logic_attribute_memory_array/_n0007<0>11
                                  13      FB5_13        (b)      (b)   
cm_addr<2>                        2       FB5_14  28    I/O      O     
io_interface_logic_io_status_en   3       FB5_15        (b)      (b)   
io_interface_logic_io_data_en     3       FB5_16        (b)      (b)   

Signals Used by Logic in Function Block
  1: N_PZ_566          10: host_addr<10>     18: host_addr<8> 
  2: N_PZ_783          11: host_addr<1>      19: host_addr<9> 
  3: cf_plus_logic_attribute_memory_array/conf<4> 
                       12: host_addr<2>      20: io_interface_logic_io_addr_en 
  4: cf_plus_logic_attribute_memory_array/conf<5> 
                       13: host_addr<3>      21: io_interface_logic_io_data_en 
  5: cf_plus_logic_attribute_memory_array/crdy_bsy_n 
                       14: host_addr<4>      22: io_interface_logic_io_status_en 
  6: cf_plus_logic_io_enab 
                       15: host_addr<5>      23: io_interface_logic_prs_state_ffd1 
  7: cf_plus_logic_mtrien_cm_addr<10> 
                       16: host_addr<6>      24: io_interface_logic_prs_state_ffd2 
  8: cf_plus_logic_soft_reset 
                       17: host_addr<7>      25: io_interface_logic_prs_state_ffd3 
  9: host_addr<0>     

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cm_addr<10>       ......X..X.............................. 2       2
cm_addr<1>        ......X...X............................. 2       2
io_interface_logic__n0183 
                  ...................XXXXXX............... 6       6
cf_plus_logic_attribute_memory_array/_n0007<4>11 
                  ..X.....XXXXXXXXXXX..................... 12      12
cf_plus_logic_attribute_memory_array/_n0007<5>17 
                  ...XX...XXXXXXXXXXX..................... 13      13
cf_plus_logic_attribute_memory_array/_n0007<7>15 
                  X...X..XXXXXXXXXXXX..................... 14      14
cf_plus_logic_attribute_memory_array/_n0007<0>11