📄 cf_plus.rpt
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io_interface_logic_io_data_done
X.........X.....X.X...XX....XXXX.X...... 11 11
cm_read_n ...X............................XXXXX... 6 6
io_interface_logic_io_data_reg<1>
X.X.X...X.XX.X.XXXX....X.X.XXXXX.X...... 19 19
cm_write_n ...X............................XXXXX... 6 6
io_interface_logic_io_data_reg<0>
X.X.X..X..XXX..XXXX....XX..XXXXX.X...... 19 19
io_interface_logic_io_addr_reg<0>
XX..X..X..XXX..XX.XX.......XXXXX.X...... 17 17
cf_plus_logic_io_write_n
....X...........................XXXXX... 6 6
cf_plus_logic_io_read_n
....X...........................XXXXX... 6 6
cf_plus_logic_am_write_n
................................XXXXX... 5 5
wait_n ......X...X.....................XX.X.... 5 5
N_PZ_705 .X........X.....XX.....X...XXXXX.X...... 11 11
io_interface_logic_io_addr_reg<2>
XX..X....XXX..XXX.X..X.....XXXXX.X...... 17 17
cf_plus_logic_am_read_n
................................XXXXX... 5 5
cf_plus_logic_cm_write_int_n
...X.X..........................XXXXX... 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB2 ***********************************
This function block is part of I/O Bank number: 2
Number of signals used by logic mapping into function block: 30
Number of function block inputs used/remaining: 30/10
Number of function block control terms used/remaining: 3/1
Number of PLA product terms used/remaining: 31/25
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB2_1 2 GTS/I/O I
io_interface_logic_io_read_n_sync 2 FB2_2 (b) (b)
cm_byte_n 3 FB2_3 3 GTS/I/O O
cm_ce_n 2 FB2_4 4 I/O O
cm_addr<0> 2 FB2_5 5 GTS/I/O O
N_PZ_694 1 FB2_6 (b) (b)
cf_plus_logic_io_inhibit_cm 3 FB2_7 (b) (b)
N_PZ_737 2 FB2_8 (b) (b)
cf_plus_logic_cm_address_state 2 FB2_9 (b) (b)
cf_plus_logic_mtrien_cm_addr<10> 2 FB2_10 (b) (b)
cf_plus_logic_mtrien_cm_addr<0> 2 FB2_11 (b) (b)
host_data_low<0> 3 FB2_12 6 GTS/I/O I/O
host_data_low<1> 3 FB2_13 7 I/O I/O
host_data_low<2> 3 FB2_14 9 I/O I/O
host_data_low<3> 3 FB2_15 10 I/O I/O
N_PZ_560 2 FB2_16 (b) (b)
Signals Used by Logic in Function Block
1: N_PZ_560 11: cf_plus_logic_am_read_n
21: cm_read_n
2: N_PZ_566 12: cf_plus_logic_cm_address_state
22: host_addr<0>
3: N_PZ_710 13: cf_plus_logic_io_enab
23: io_interface_logic_io_data_r<0>
4: N_PZ_737 14: cf_plus_logic_io_inhibit_cm
24: io_interface_logic_io_data_r<1>
5: ce1_n 15: cf_plus_logic_io_read_n
25: io_interface_logic_io_data_r<2>
6: ce2_n 16: cf_plus_logic_mtrien_cm_addr<0>
26: io_interface_logic_io_data_r<3>
7: cf_plus_logic_am_data_r<0>
17: cm_data<0>.PIN 27: io_interface_logic_io_read_valid
8: cf_plus_logic_am_data_r<1>
18: cm_data<1>.PIN 28: iord_n
9: cf_plus_logic_am_data_r<2>
19: cm_data<2>.PIN 29: iowr_n
10: cf_plus_logic_am_data_r<3>
20: cm_data<3>.PIN 30: reg_n
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
io_interface_logic_io_read_n_sync
.X............X......................... 2 2
cm_byte_n .X..XX.....X.................X.......... 5 5
cm_ce_n .XX........X.................X.......... 4 4
cm_addr<0> ....X........X.X.....X.......X.......... 5 5
N_PZ_694 ....XX..............X................... 3 3
cf_plus_logic_io_inhibit_cm
.XX..........X.............XX........... 5 5
N_PZ_737 ....XX....X.........XX.................. 5 5
cf_plus_logic_cm_address_state
.XX..........X...............X.......... 4 4
cf_plus_logic_mtrien_cm_addr<10>
.XX..........X...............X.......... 4 4
cf_plus_logic_mtrien_cm_addr<0>
.XX..........X...............X.......... 4 4
host_data_low<0> X..XXXX...X.....X....XX................. 9 9
host_data_low<1> X..XXX.X..X......X...X.X................ 9 9
host_data_low<2> X..XXX..X.X.......X..X..X............... 9 9
host_data_low<3> X..XXX...XX........X.X...X.............. 9 9
N_PZ_560 ....XX....X.........XX.................. 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
*********************************** FB3 ***********************************
This function block is part of I/O Bank number: 2
Number of signals used by logic mapping into function block: 38
Number of function block inputs used/remaining: 38/2
Number of function block control terms used/remaining: 3/1
Number of PLA product terms used/remaining: 44/12
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
dsp_data<3> 4 FB3_1 136 I/O I/O
dsp_data<4> 4 FB3_2 135 I/O I/O
dsp_data<5> 4 FB3_3 134 I/O I/O
io_interface_logic_io_addr_reg<7> 4 FB3_4 (b) (b)
io_interface_logic_io_read_valid 2 FB3_5 133 I/O I
io_interface_logic_io_data_reg<7> 4 FB3_6 (b) (b)
io_interface_logic_io_addr_reg<6> 4 FB3_7 (b) (b)
io_interface_logic_io_data_reg<6> 4 FB3_8 (b) (b)
io_interface_logic_io_addr_reg<5> 4 FB3_9 (b) (b)
io_interface_logic_io_addr_reg<4> 4 FB3_10 (b) (b)
io_interface_logic_io_addr_reg<3> 4 FB3_11 (b) (b)
io_interface_logic_io_data_reg<5> 4 FB3_12 (b) (b)
io_interface_logic_io_data_reg<4> 4 FB3_13 (b) (b)
io_interface_logic_dsp_data_done 4 FB3_14 132 I/O I
io_interface_logic_io_data_reg<3> 4 FB3_15 (b) (b)
N_PZ_703 2 FB3_16 131 I/O I
Signals Used by Logic in Function Block
1: N_PZ_566 14: host_data_low<5>.PIN
27: io_interface_logic_io_data_en
2: N_PZ_703 15: host_data_low<6>.PIN
28: io_interface_logic_io_data_reg<3>
3: N_PZ_705 16: host_data_low<7>.PIN
29: io_interface_logic_io_data_reg<4>
4: cf_plus_logic_io_enab
17: io_interface_logic__n0185
30: io_interface_logic_io_data_reg<5>
5: dsp_data<3>.PIN 18: io_interface_logic_dsp_addr_en
31: io_interface_logic_io_data_reg<6>
6: dsp_data<4>.PIN 19: io_interface_logic_dsp_data_done
32: io_interface_logic_io_data_reg<7>
7: dsp_data<5>.PIN 20: io_interface_logic_dsp_data_en
33: io_interface_logic_io_status_reg<6>
8: dsp_data<6>.PIN 21: io_interface_logic_io_addr_en
34: io_interface_logic_io_status_reg<7>
9: dsp_data<7>.PIN 22: io_interface_logic_io_addr_reg<3>
35: io_interface_logic_prs_state_ffd1
10: dsp_ioms_n 23: io_interface_logic_io_addr_reg<4>
36: io_interface_logic_prs_state_ffd2
11: dsp_wr_n 24: io_interface_logic_io_addr_reg<5>
37: io_interface_logic_prs_state_ffd3
12: host_data_low<3>.PIN
25: io_interface_logic_io_addr_reg<6>
38: iowr_n
13: host_data_low<4>.PIN
26: io_interface_logic_io_addr_reg<7>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
dsp_data<3> .........X......XX.X.X.....X......XXX... 9 9
dsp_data<4> .........X......XX.X..X.....X.....XXX... 9 9
dsp_data<5> .........X......XX.X...X.....X....XXX... 9 9
io_interface_logic_io_addr_reg<7>
XX.X....XXX....X.XX.X....X......XXXXXX.. 17 17
io_interface_logic_io_read_valid
X.................................XXX... 4 4
io_interface_logic_io_data_reg<7>
X.XX....XXX....X.XXXX.....X....XXXXXXX.. 19 19
io_interface_logic_io_addr_reg<6>
XX.X...X.XX...X..XX.X...X.......XXXXXX.. 17 17
io_interface_logic_io_data_reg<6>
X.XX...X.XX...X..XXXX.....X...X.XXXXXX.. 19 19
io_interface_logic_io_addr_reg<5>
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