📄 cf_plus.rpt
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io_interface_logic_io_data_r<3> 3 8 FB6_5 (b) (b) LATCH RESET
io_interface_logic_io_data_r<4> 3 8 FB6_3 (b) (b) LATCH RESET
io_interface_logic_io_data_r<5> 3 8 FB11_7 (b) (b) LATCH RESET
io_interface_logic_io_data_r<6> 4 10 FB6_8 (b) (b) LATCH RESET
io_interface_logic_io_data_r<7> 4 10 FB6_7 (b) (b) LATCH RESET
io_interface_logic_io_data_reg<0> 4 19 FB1_7 (b) (b) DFF RESET
io_interface_logic_io_data_reg<1> 4 19 FB1_5 (b) (b) DFF RESET
io_interface_logic_io_data_reg<2> 4 19 FB1_1 (b) (b) DFF RESET
io_interface_logic_io_data_reg<3> 4 19 FB3_15 (b) (b) DFF RESET
io_interface_logic_io_data_reg<4> 4 19 FB3_13 (b) (b) DFF RESET
io_interface_logic_io_data_reg<5> 4 19 FB3_12 (b) (b) DFF RESET
io_interface_logic_io_data_reg<6> 4 19 FB3_8 (b) (b) DFF RESET
io_interface_logic_io_data_reg<7> 4 19 FB3_6 (b) (b) DFF RESET
io_interface_logic_io_irq_n 5 9 FB7_8 (b) (b) DFF RESET
io_interface_logic_io_read_n_sync 2 2 FB2_2 (b) (b) DFF RESET
io_interface_logic_io_read_valid 2 4 FB3_5 133 I/O I DFF RESET
io_interface_logic_io_status_en 3 18 FB5_15 (b) (b) DFF RESET
io_interface_logic_io_status_reg<0> 4 8 FB8_10 (b) (b) TFF RESET
io_interface_logic_io_status_reg<1> 4 8 FB8_9 (b) (b) TFF RESET
io_interface_logic_io_status_reg<6> 3 3 FB8_15 (b) (b) DEFF RESET
io_interface_logic_io_status_reg<7> 3 3 FB8_14 (b) (b) DEFF RESET
io_interface_logic_io_write_n_sync 2 2 FB7_10 (b) (b) DFF RESET
io_interface_logic_irq_count<0> 2 2 FB8_16 (b) (b) TFF RESET
io_interface_logic_irq_count<1> 2 3 FB7_16 19 I/O I TFF RESET
io_interface_logic_irq_count<2> 2 4 FB7_1 (b) (b) TFF RESET
io_interface_logic_irq_count<3> 2 5 FB7_2 (b) (b) TFF RESET
io_interface_logic_irq_count<4> 2 6 FB7_3 (b) (b) TFF RESET
io_interface_logic_irq_count_clr 2 3 FB7_9 (b) (b) DFF RESET
io_interface_logic_irq_count_en 5 10 FB7_7 (b) (b) DFF RESET
io_interface_logic_prs_state_ffd1 6 11 FB8_7 (b) (b) DFF RESET
io_interface_logic_prs_state_ffd2 7 12 FB8_4 (b) (b) DFF RESET
io_interface_logic_prs_state_ffd3 6 7 FB8_13 52 I/O I DFF RESET
iois16_n 0 0 FB6_16 FAST 43 I/O O LVCMOS33
ireq_n 3 5 FB10_16 FAST 101 I/O O LVCMOS33
level_pulse_n 3 15 FB4_12 17 I/O I TFF RESET
stschg_n 1 4 FB10_14 FAST 102 I/O O LVCMOS33
vcc1 0 0 FB7_5 FAST 26 I/O O LVCMOS33
vcc2 0 0 FB7_6 FAST 25 I/O O LVCMOS33
vs1 0 0 FB11_15 FAST 129 I/O O LVCMOS33
vs2 0 0 FB7_11 FAST 24 I/O O LVCMOS33
wait_n 3 5 FB1_12 FAST 139 I/O O LVCMOS33
** INPUTS **
Signal Loc Pin Pin Pin Reg I/O I/O
Name # Type Use Use STD Style
ce1_n FB2_1 2 GTS/I/O I LVCMOS33 S/PU
ce2_n FB3_14 132 I/O I LVCMOS33 S/PU
cm_sts FB7_16 19 I/O I LVCMOS33
cm_wait FB1_13 138 I/O I LVCMOS33
dsp_addr<0> FB3_16 131 I/O I LVCMOS33
dsp_addr<10> FB8_3 46 I/O I LVCMOS33
dsp_addr<1> FB8_5 48 I/O I LVCMOS33
dsp_addr<2> FB8_6 49 I/O I LVCMOS33
dsp_addr<3> FB8_11 50 I/O I LVCMOS33
dsp_addr<4> FB8_12 51 I/O I LVCMOS33
dsp_addr<5> FB8_13 52 I/O I LVCMOS33
dsp_addr<6> FB14_13 66 I/O I LVCMOS33
dsp_addr<7> FB14_3 70 I/O I LVCMOS33
dsp_addr<8> FB14_16 61 I/O I LVCMOS33
dsp_addr<9> FB14_4 69 I/O I LVCMOS33
dsp_clk FB5_4 32 GCK/I/O GCK LVCMOS33
dsp_ioms_n FB8_1 44 I/O I LVCMOS33
dsp_rd_n FB8_2 45 I/O I LVCMOS33
dsp_wr_n FB1_14 137 I/O I LVCMOS33
host_addr<0> FB4_2 12 I/O I LVCMOS33
host_addr<10> FB4_3 13 I/O I LVCMOS33
host_addr<1> FB4_4 14 I/O I LVCMOS33
host_addr<2> FB4_5 15 I/O I LVCMOS33
host_addr<3> FB4_6 16 I/O I LVCMOS33
host_addr<4> FB4_12 17 I/O I LVCMOS33
host_addr<5> FB4_14 18 I/O I LVCMOS33
host_addr<6> FB14_14 64 I/O I LVCMOS33
host_addr<7> FB14_2 71 I/O I LVCMOS33
host_addr<8> FB15_2 83 I/O I LVCMOS33
host_addr<9> FB15_11 85 I/O I LVCMOS33
iord_n FB15_12 86 I/O I LVCMOS33 S/PU
iowr_n FB3_5 133 I/O I LVCMOS33 S/PU
oe_n FB15_13 87 I/O I LVCMOS33 S/PU
reg_n FB15_14 88 I/O I LVCMOS33 S/PU
reset FB1_3 143 GSR/I/O GSR/I LVCMOS33
we_n FB5_6 30 GCK/I/O GCK/I LVCMOS33 S/PU
End of Resources Used by Successfully Mapped Logic
Legend:
I/O Style - OD - OpenDrain
- PU - Pullup
- KPR - Keeper
- S - SchmittTrigger
- DG - DataGate
Reg Use - LATCH - Transparent latch
- DFF - D-flip-flop
- DEFF - D-flip-flop with clock enable
- TFF - T-flip-flop
- TDFF - Dual-edge-triggered T-flip-flop
- DDFF - Dual-edge-triggered flip-flop
- DDEFF - Dual-edge-triggered flip-flop with clock enable
/S (after any above flop/latch type) indicates initial state is Set
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 16 37 37 35 3/0 6
FB2 15 30 30 31 3/4 8
FB3 16 38 38 44 0/3 6
FB4 15 38 38 53 1/0 8
FB5 10 25 25 56 3/0 5
FB6 16 30 30 41 3/5 8
FB7 16 12 12 19 7/0 8
FB8 16 38 38 45 0/0 8
FB9 13 34 34 33 0/8 8
FB10 14 26 26 56 9/0 9
FB11 12 27 27 22 4/4 8
FB12 8 11 11 14 0/6 6
FB13 8 9 9 9 0/8 8
FB14 2 3 3 3 0/2 8
FB15 0 0 0 0 0/0 7
FB16 0 0 0 0 0/0 7
---- ----- ----- -----
177 461 33/40 118
*********************************** FB1 ***********************************
This function block is part of I/O Bank number: 2
Number of signals used by logic mapping into function block: 37
Number of function block inputs used/remaining: 37/3
Number of function block control terms used/remaining: 1/3
Number of PLA product terms used/remaining: 35/21
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
io_interface_logic_io_data_reg<2> 4 FB1_1 (b) (b)
io_interface_logic_io_addr_reg<1> 4 FB1_2 (b) (b)
io_interface_logic_io_data_done 5 FB1_3 143 GSR/I/O GSR/I
cm_read_n 1 FB1_4 142 I/O O
io_interface_logic_io_data_reg<1> 4 FB1_5 (b) (b)
cm_write_n 1 FB1_6 140 I/O O
io_interface_logic_io_data_reg<0> 4 FB1_7 (b) (b)
io_interface_logic_io_addr_reg<0> 4 FB1_8 (b) (b)
cf_plus_logic_io_write_n 1 FB1_9 (b) (b)
cf_plus_logic_io_read_n 1 FB1_10 (b) (b)
cf_plus_logic_am_write_n 1 FB1_11 (b) (b)
wait_n 3 FB1_12 139 I/O O
N_PZ_705 2 FB1_13 138 I/O I
io_interface_logic_io_addr_reg<2> 4 FB1_14 137 I/O I
cf_plus_logic_am_read_n 1 FB1_15 (b) (b)
cf_plus_logic_cm_write_int_n 2 FB1_16 (b) (b)
Signals Used by Logic in Function Block
1: N_PZ_566 14: host_data_low<1>.PIN
26: io_interface_logic_io_data_reg<1>
2: N_PZ_703 15: host_data_low<2>.PIN
27: io_interface_logic_io_data_reg<2>
3: N_PZ_705 16: io_interface_logic_dsp_addr_en
28: io_interface_logic_io_status_reg<6>
4: cf_plus_logic_cm_address_state
17: io_interface_logic_dsp_data_done
29: io_interface_logic_io_status_reg<7>
5: cf_plus_logic_io_enab
18: io_interface_logic_dsp_data_en
30: io_interface_logic_prs_state_ffd1
6: cm_ce_n 19: io_interface_logic_io_addr_en
31: io_interface_logic_prs_state_ffd2
7: cm_wait 20: io_interface_logic_io_addr_reg<0>
32: io_interface_logic_prs_state_ffd3
8: dsp_data<0>.PIN 21: io_interface_logic_io_addr_reg<1>
33: iord_n
9: dsp_data<1>.PIN 22: io_interface_logic_io_addr_reg<2>
34: iowr_n
10: dsp_data<2>.PIN 23: io_interface_logic_io_data_done
35: oe_n
11: dsp_ioms_n 24: io_interface_logic_io_data_en
36: reg_n
12: dsp_wr_n 25: io_interface_logic_io_data_reg<0>
37: we_n
13: host_data_low<0>.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
io_interface_logic_io_data_reg<2>
X.X.X....XXX..XXXXX....X..XXXXXX.X...... 19 19
io_interface_logic_io_addr_reg<1>
XX..X...X.XX.X.XX.X.X......XXXXX.X...... 17 17
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