📄 cf_plus.rpt
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cpldfit: version F.30a Xilinx Inc.
Fitter Report
Design Name: cf_plus Date: 6-27-2003, 9:46AM
Device Used: XC2C256-7-TQ144
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
177/256 ( 69%) 461 /896 ( 51%) 105/256 ( 41%) 109/118 ( 92%) 358/640 ( 56%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 33 33 | I/O : 101 7
Output : 33 33 | GCK/IO : 3 0
Bidirectional : 40 40 | GTS/IO : 4 0
GCK : 2 2 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 109 109
MACROCELL RESOURCES:
Total Macrocells Available 256
Registered Macrocells 105
Non-registered Macrocell driving I/O 50
GLOBAL RESOURCES:
Signal 'we_n' mapped onto global clock net GCK0.
Signal 'dsp_clk' mapped onto global clock net GCK1.
Signal 'cf_plus_logic__n0112_MC.GLB' mapped onto global output enable net GTS2.
Signal 'reset' mapped onto global set/reset net GSR.
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Slew Pin Pin Pin Reg I/O I/O Reg Init
Name Pt Used Rate # Type Use Use STD Style State
N_PZ_560 2 5 FB2_16 (b) (b)
N_PZ_566 1 2 FB9_8 (b) (b)
N_PZ_694 1 3 FB2_6 (b) (b)
N_PZ_703 2 10 FB3_16 131 I/O I
N_PZ_705 2 11 FB1_13 138 I/O I
N_PZ_710 1 2 FB9_16 (b) (b)
N_PZ_737 2 5 FB2_8 (b) (b)
N_PZ_769 2 5 FB8_2 45 I/O I
N_PZ_783 3 6 FB8_12 51 I/O I
N_PZ_796 2 4 FB8_1 44 I/O I
bvd2 0 0 FB6_14 FAST 41 I/O O LVCMOS33
cd1 0 0 FB7_12 FAST 23 I/O O LVCMOS33
cd2 0 0 FB7_13 FAST 22 I/O O LVCMOS33
cf_plus_logic_am_data_r<0> 4 3 FB9_11 (b) (b) LATCH RESET
cf_plus_logic_am_data_r<1> 4 3 FB12_10 (b) (b) LATCH RESET
cf_plus_logic_am_data_r<2> 4 3 FB9_10 (b) (b) LATCH RESET
cf_plus_logic_am_data_r<3> 4 3 FB10_10 (b) (b) LATCH RESET
cf_plus_logic_am_data_r<4> 4 3 FB10_9 (b) (b) LATCH RESET
cf_plus_logic_am_data_r<5> 4 3 FB11_10 (b) (b) LATCH RESET
cf_plus_logic_am_data_r<6> 4 3 FB11_9 (b) (b) LATCH RESET
cf_plus_logic_am_data_r<7> 4 3 FB12_16 (b) (b) LATCH RESET
cf_plus_logic_am_read_n 1 5 FB1_15 (b) (b) DFF RESET
cf_plus_logic_am_write_n 1 5 FB1_11 (b) (b) DFF RESET
cf_plus_logic_attribute_memory_array/_n0007<0>11 13 12 FB5_13 (b) (b)
cf_plus_logic_attribute_memory_array/_n0007<1> 19 16 FB10_15 (b) (b)
cf_plus_logic_attribute_memory_array/_n0007<2>13 14 12 FB10_13 (b) (b)
cf_plus_logic_attribute_memory_array/_n0007<3>13 12 12 FB10_11 (b) (b)
cf_plus_logic_attribute_memory_array/_n0007<4>11 16 12 FB5_10 (b) (b)
cf_plus_logic_attribute_memory_array/_n0007<5>17 10 13 FB5_11 (b) (b)
cf_plus_logic_attribute_memory_array/_n0007<6>12 13 13 FB4_5 15 I/O I
cf_plus_logic_attribute_memory_array/_n0007<7>15 12 14 FB5_12 (b) (b)
cf_plus_logic_attribute_memory_array/conf<1> 3 15 FB4_13 (b) (b) TFF RESET
cf_plus_logic_attribute_memory_array/conf<3> 3 15 FB4_10 (b) (b) TFF RESET
cf_plus_logic_attribute_memory_array/conf<4> 3 15 FB4_9 (b) (b) TFF RESET
cf_plus_logic_attribute_memory_array/conf<5> 3 15 FB4_8 (b) (b) TFF RESET
cf_plus_logic_attribute_memory_array/crdy_bsy_n 3 5 FB9_9 (b) (b) DFF RESET
cf_plus_logic_attribute_memory_array/host_crdy_bsy_n 3 15 FB4_7 (b) (b) TFF RESET
cf_plus_logic_attribute_memory_array/mrdy_bsy_n 3 15 FB4_11 (b) (b) TFF RESET
cf_plus_logic_attribute_memory_array/sigchg 3 15 FB4_14 18 I/O I TFF RESET
cf_plus_logic_cm_address_state 2 4 FB2_9 (b) (b) DFF RESET
cf_plus_logic_cm_write_int_n 2 7 FB1_16 (b) (b) DFF RESET
cf_plus_logic_io_enab 3 15 FB4_16 (b) (b) TFF RESET
cf_plus_logic_io_inhibit_cm 3 5 FB2_7 (b) (b) DFF RESET
cf_plus_logic_io_ireq_route 3 15 FB4_6 16 I/O I TFF RESET
cf_plus_logic_io_read_n 1 6 FB1_10 (b) (b) DFF RESET
cf_plus_logic_io_write_n 1 6 FB1_9 (b) (b) DFF RESET
cf_plus_logic_mtrien_cm_addr<0> 2 4 FB2_11 (b) (b) DFF RESET
cf_plus_logic_mtrien_cm_addr<10> 2 4 FB2_10 (b) (b) DFF RESET
cf_plus_logic_soft_reset 2 14 FB4_15 (b) (b) TFF RESET
cm_addr<0> 2 5 FB2_5 FAST 5 GTS/I/O O DFF LVCMOS33 RESET
cm_addr<10> 2 2 FB5_2 FAST 33 I/O O DFF LVCMOS33 RESET
cm_addr<1> 2 2 FB5_5 FAST 31 I/O O DFF LVCMOS33 RESET
cm_addr<2> 2 2 FB5_14 FAST 28 I/O O DFF LVCMOS33 RESET
cm_addr<3> 2 2 FB10_1 FAST 111 I/O O DFF LVCMOS33 RESET
cm_addr<4> 2 2 FB10_2 FAST 110 I/O O DFF LVCMOS33 RESET
cm_addr<5> 2 2 FB10_3 FAST 107 I/O O DFF LVCMOS33 RESET
cm_addr<6> 2 2 FB10_4 FAST 106 I/O O DFF LVCMOS33 RESET
cm_addr<7> 2 2 FB10_5 FAST 105 I/O O DFF LVCMOS33 RESET
cm_addr<8> 2 2 FB10_6 FAST 104 I/O O DFF LVCMOS33 RESET
cm_addr<9> 2 2 FB10_12 FAST 103 I/O O DFF LVCMOS33 RESET
cm_byte_n 3 5 FB2_3 FAST 3 GTS/I/O O DFF LVCMOS33 RESET
cm_ce_n 2 4 FB2_4 FAST 4 I/O O DFF LVCMOS33 RESET
cm_data<0> 2 2 FB12_2 FAST 100 I/O I/O LVCMOS33
cm_data<10> 2 2 FB12_11 FAST 98 I/O I/O LVCMOS33
cm_data<11> 2 2 FB12_12 FAST 97 I/O I/O LVCMOS33
cm_data<12> 2 2 FB12_13 FAST 96 I/O I/O LVCMOS33
cm_data<13> 2 2 FB12_14 FAST 95 I/O I/O LVCMOS33
cm_data<14> 2 2 FB12_15 FAST 94 I/O I/O LVCMOS33
cm_data<15> 2 2 FB13_1 FAST 75 I/O I/O LVCMOS33
cm_data<1> 2 2 FB13_2 FAST 76 I/O I/O LVCMOS33
cm_data<2> 2 2 FB13_3 FAST 77 I/O I/O LVCMOS33
cm_data<3> 2 2 FB13_5 FAST 78 I/O I/O LVCMOS33
cm_data<4> 2 2 FB13_6 FAST 79 I/O I/O LVCMOS33
cm_data<5> 2 2 FB13_12 FAST 80 I/O I/O LVCMOS33
cm_data<6> 2 2 FB13_13 FAST 81 I/O I/O LVCMOS33
cm_data<7> 2 2 FB13_14 FAST 82 I/O I/O LVCMOS33
cm_data<8> 2 2 FB14_1 FAST 74 I/O I/O LVCMOS33
cm_data<9> 2 2 FB14_6 FAST 68 I/O I/O LVCMOS33
cm_read_n 1 6 FB1_4 FAST 142 I/O O DFF LVCMOS33 RESET
cm_reset 1 2 FB11_16 FAST 130 I/O O LVCMOS33
cm_write_n 1 6 FB1_6 FAST 140 I/O O DFF LVCMOS33 RESET
csel 0 0 FB6_15 FAST 42 I/O O LVCMOS33
dsp_data<0> 5 11 FB6_1 FAST 34 I/O I/O LATCH LVCMOS33 RESET
dsp_data<1> 5 11 FB6_2 FAST 35 CDR/I/O I/O LATCH LVCMOS33 RESET
dsp_data<2> 4 9 FB6_13 FAST 40 I/O I/O LATCH LVCMOS33 RESET
dsp_data<3> 4 9 FB3_1 FAST 136 I/O I/O LATCH LVCMOS33 RESET
dsp_data<4> 4 9 FB3_2 FAST 135 I/O I/O LATCH LVCMOS33 RESET
dsp_data<5> 4 9 FB3_3 FAST 134 I/O I/O LATCH LVCMOS33 RESET
dsp_data<6> 5 11 FB6_4 FAST 38 GCK/I/O I/O LATCH LVCMOS33 RESET
dsp_data<7> 5 11 FB6_12 FAST 39 DGE/I/O I/O LATCH LVCMOS33 RESET
gnd1 0 0 FB7_14 FAST 21 I/O O LVCMOS33
gnd2 0 0 FB7_15 FAST 20 I/O O LVCMOS33
gnd3 0 0 FB11_13 FAST 126 I/O O LVCMOS33
gnd4 0 0 FB11_14 FAST 128 I/O O LVCMOS33
host_data_high<0> 3 5 FB11_5 FAST 120 I/O I/O LVCMOS33
host_data_high<1> 3 5 FB11_6 FAST 121 I/O I/O LVCMOS33
host_data_high<2> 3 5 FB11_11 FAST 124 I/O I/O LVCMOS33
host_data_high<3> 3 5 FB11_12 FAST 125 I/O I/O LVCMOS33
host_data_high<4> 3 5 FB9_12 FAST 116 I/O I/O LVCMOS33
host_data_high<5> 3 5 FB9_13 FAST 117 I/O I/O LVCMOS33
host_data_high<6> 3 5 FB9_14 FAST 118 I/O I/O LVCMOS33
host_data_high<7> 3 5 FB9_15 FAST 119 I/O I/O LVCMOS33
host_data_low<0> 3 9 FB2_12 FAST 6 GTS/I/O I/O LVCMOS33
host_data_low<1> 3 9 FB2_13 FAST 7 I/O I/O LVCMOS33
host_data_low<2> 3 9 FB2_14 FAST 9 I/O I/O LVCMOS33
host_data_low<3> 3 9 FB2_15 FAST 10 I/O I/O LVCMOS33
host_data_low<4> 3 9 FB9_1 FAST 112 I/O I/O LVCMOS33
host_data_low<5> 3 9 FB9_2 FAST 113 I/O I/O LVCMOS33
host_data_low<6> 3 9 FB9_4 FAST 114 I/O I/O LVCMOS33
host_data_low<7> 3 9 FB9_6 FAST 115 I/O I/O LVCMOS33
inpack_n 2 13 FB4_1 FAST 11 I/O O LVCMOS33
io_interface_logic__n0167 2 5 FB11_8 (b) (b)
io_interface_logic__n0170 2 7 FB8_8 (b) (b)
io_interface_logic__n0183 2 6 FB5_9 (b) (b)
io_interface_logic__n0185 2 6 FB6_11 (b) (b)
io_interface_logic__n0187 2 7 FB7_4 (b) (b) TFF RESET
io_interface_logic_dsp_addr_en 3 17 FB8_11 50 I/O I DFF RESET
io_interface_logic_dsp_address_match 4 16 FB8_5 48 I/O I DFF RESET
io_interface_logic_dsp_data_done 4 9 FB3_14 132 I/O I DFF RESET
io_interface_logic_dsp_data_en 3 17 FB8_6 49 I/O I DFF RESET
io_interface_logic_dsp_status_en 3 17 FB8_3 46 I/O I DFF RESET
io_interface_logic_io_addr_en 3 18 FB4_3 13 I/O I DFF RESET
io_interface_logic_io_addr_reg<0> 4 17 FB1_8 (b) (b) DFF RESET
io_interface_logic_io_addr_reg<1> 4 17 FB1_2 (b) (b) DFF RESET
io_interface_logic_io_addr_reg<2> 4 17 FB1_14 137 I/O I DFF RESET
io_interface_logic_io_addr_reg<3> 4 17 FB3_11 (b) (b) DFF RESET
io_interface_logic_io_addr_reg<4> 4 17 FB3_10 (b) (b) DFF RESET
io_interface_logic_io_addr_reg<5> 4 17 FB3_9 (b) (b) DFF RESET
io_interface_logic_io_addr_reg<6> 4 17 FB3_7 (b) (b) DFF RESET
io_interface_logic_io_addr_reg<7> 4 17 FB3_4 (b) (b) DFF RESET
io_interface_logic_io_address_match 4 17 FB4_4 14 I/O I DFF RESET
io_interface_logic_io_data_done 5 11 FB1_3 143 GSR/I/O GSR/I DFF RESET
io_interface_logic_io_data_en 3 18 FB5_16 (b) (b) DFF RESET
io_interface_logic_io_data_r<0> 4 10 FB6_10 (b) (b) LATCH RESET
io_interface_logic_io_data_r<1> 4 10 FB6_9 (b) (b) LATCH RESET
io_interface_logic_io_data_r<2> 3 8 FB6_6 (b) (b) LATCH RESET
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