cf_plus_control.vhd

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

	--******************************* Reset Logic ************************************
	card_reset <= soft_reset or reset;		-- soft reset form SRESET bit in COR and the
														-- reset pin.  Both signals are active HIGH
														-- per the CF+ spec.  Therefore card_reset is
														-- active HIGH.
	

	--**************************** Card Enable Logic *********************************
 	-- 8/16-bit mode 	(even byte)
 	eight_even			<= '1' when (ce1_n = '0' and ce2_n = '1' and host_addr(0) = '0') else '0';
 	
 	-- 8-bit mode 		(odd byte)
	eight_odd			<= '1' when (ce1_n = '0' and ce2_n = '1' and host_addr(0) = '1') else '0';
	
	-- 16-bit mode 	(odd byte only)
	sixteen_odd			<= '1' when (ce1_n = '1' and ce2_n = '0') else '0';
	
	-- 16-bit mode 	(even & odd byte)
	sixteen_even_odd	<= '1' when (ce1_n = '0' and ce2_n = '0') else '0';


	--*************************** Read/Write Detect *********************************
	read_write_detect: process (reset, io_clk, reg_n, iord_n, iowr_n, oe_n, we_n, cm_ce_n, io_enab, cm_address_state)
	begin
		if reset = RESET_ACTIVE then
		
			cm_read_n		<= '1';
			cm_write_n		<= '1';
			cm_write_int_n	<= '1';
			am_read_n		<= '1';
			am_write_n		<= '1';
			io_read_n		<= '1';
			io_write_n		<= '1';
			--	io_write_int_n <= '1';
			
		elsif io_clk'event and io_clk = '1' then
	
			----------------------------------------------------------
			-- ***************** Common Memory access ****************
			----------------------------------------------------------
			-- read
			if (reg_n = '1' and iord_n = '1' and iowr_n = '1' and oe_n = '0' and we_n ='1' and cm_address_state = '1') then
				cm_read_n		<= '0';
				cm_write_n		<= '1';
				am_read_n		<= '1';
				am_write_n		<= '1';
				io_read_n		<= '1';
				io_write_n		<= '1';
				
			-- write
			elsif (reg_n = '1' and iord_n = '1' and iowr_n = '1' and oe_n = '1' and we_n ='0' and cm_address_state = '1') then
				cm_read_n		<= '1';
				cm_write_n		<= '0';
				am_read_n		<= '1';
				am_write_n		<= '1';
				io_read_n		<= '1';
				io_write_n		<= '1';
				
			----------------------------------------------------------
			-- *************** Attribute Memory access ***************
			----------------------------------------------------------
			-- read
			elsif (reg_n = '0' and iord_n = '1' and iowr_n = '1' and oe_n = '0' and we_n ='1') then
				cm_read_n		<= '1';
				cm_write_n		<= '1';
				am_read_n		<= '0';
				am_write_n		<= '1';
				io_read_n		<= '1';
				io_write_n		<= '1';
				
			-- write
			elsif (reg_n = '0' and iord_n = '1' and iowr_n = '1' and oe_n = '1' and we_n ='0') then
				cm_read_n		<= '1';
				cm_write_n		<= '1';
				am_read_n		<= '1';
				am_write_n		<= '0';
				io_read_n		<= '1';
				io_write_n		<= '1';

			----------------------------------------------------------
			-- **************** I/O Interface access *****************
			----------------------------------------------------------
			-- read
			elsif (reg_n = '0' and iord_n = '0' and iowr_n = '1' and oe_n = '1' and we_n ='1' and io_enab = '1') then
				cm_read_n		<= '1';
				cm_write_n		<= '1';
				am_read_n		<= '1';
				am_write_n		<= '1';
				io_read_n		<= '0';
				io_write_n		<= '1';
				
			-- write
			elsif (reg_n = '0' and iord_n = '1' and iowr_n = '0' and oe_n = '1' and we_n ='1' and io_enab = '1') then
				cm_read_n		<= '1';
				cm_write_n		<= '1';
				am_read_n		<= '1';
				am_write_n		<= '1';
				io_read_n		<= '1';
				io_write_n		<= '0';
			
			else
				cm_read_n		<= '1';
				cm_write_n		<= '1';
				am_read_n		<= '1';
				am_write_n		<= '1';
				io_read_n		<= '1';
				io_write_n		<= '1';
			end if;

		
			if (reg_n = '1' and iord_n = '1' and iowr_n = '1' and oe_n = '1' and (we_n ='0' or cm_ce_n = '0') and cm_address_state = '1') then
				cm_write_int_n	<= '0';
				--	io_write_int_n <= '1';

			else
				cm_write_int_n	<= '1';

			end if;				
	
		end if;
	end process;
	
	
	inhibit_cm_access: process(card_reset, io_clk, iowr_n, iord_n, ce1_n, ce2_n, io_inhibit_cm)
	begin
		if card_reset = RESET_ACTIVE then
			io_inhibit_cm <= '0';
		elsif io_clk'event and io_clk = '1' then
			if ((iowr_n = '0' or iord_n = '0') and io_inhibit_cm = '0') then
				io_inhibit_cm <= '1';
			elsif (ce1_n = '1' and ce2_n = '1' and io_inhibit_cm = '1') then
				io_inhibit_cm <= '0';
			else
				io_inhibit_cm <= io_inhibit_cm;
			end if;
		end if;
	end process;


	--**************************** Data Tranceiver **********************************
	
	----------------------------------------------------------		
	-- ************************ Read *************************
	----------------------------------------------------------		
	host_data_low <= 
	
			-- Attribute Memory
			am_data_r when (am_read_n = '0' and eight_even = '1') else
	
 			-- Common Memory 8/16-bit mode 	(even byte)
 			cm_data(7 downto 0) when (cm_read_n = '0' and eight_even = '1') else
 		
			-- Common Memory 8-bit mode 		(odd byte)
			cm_data(7 downto 0) when (cm_read_n = '0' and eight_odd = '1') else
		
			-- Common Memory 16-bit mode 		(even (LOW) & odd (HIGH) byte)
			cm_data(7 downto 0) when (cm_read_n = '0' and sixteen_even_odd = '1') else
		
 			-- I/O Interface 8-bit mode (and 16 bit when enabled)		(even byte)
 			io_data_r(7 downto 0) when (io_read_valid = '1' and io_read_n = '0' and eight_even = '1' and io_enab = '1') else
 		
			-- I/O Interface 8-bit mode 		(odd byte)
			io_data_r(7 downto 0) when (io_read_valid = '1' and io_read_n = '0' and eight_odd = '1' and io_enab = '1') else
		
			--########################################################
			-- The below is used for a 16 bit I/O space configuration
			--			-- I/O Interface 16-bit mode 		(even (LOW) & odd (HIGH) byte)
			--			io_data_r(7 downto 0) when (io_read_valid = '1' and io_read_n = '0' and sixteen_even_odd = '1' and io_enab = '1') else
			--########################################################
		
			-- Standby Mode/Invalid State
			(others => 'Z');
		
	----------------------------------------------------------
	host_data_high <= 
	
			-- Common Memory 16-bit mode 		(odd byte only)
			cm_data(7 downto 0) when (cm_read_n = '0' and sixteen_odd = '1') else
		
			-- Common Memory 16-bit mode 		(even (LOW) & odd (HIGH) byte)
			cm_data(15 downto 8) when (cm_read_n = '0' and sixteen_even_odd = '1') else
		
			--########################################################
			-- The below is used for a 16 bit I/O space configuration
			--			-- I/O Interface 16-bit mode 		(odd byte only)
			--			io_data_r(15 downto 8) when (io_read_valid = '1' and io_read_n = '0' and sixteen_odd = '1' and io_enab = '1') else
			--		
			--			-- I/O Interface 16-bit mode 		(even (LOW) & odd (HIGH) byte)
			--			io_data_r(15 downto 8) when (io_read_valid = '1' and io_read_n = '0' and sixteen_even_odd = '1' and io_enab = '1') else
			--########################################################
		
			-- Standby Mode/Invalid State
			(others => 'Z');

	----------------------------------------------------------		
	-- ************************ Write ************************
	----------------------------------------------------------		
	-- Attribute Memory			
	am_data_w <= host_data_low when (am_write_n = '0') else
		(others => '0');

	-- Common Memory
	cm_data(7 downto 0) <= host_data_low when (cm_write_int_n = '0') else
		(others => 'Z');
	cm_data(15 downto 8) <= host_data_high when (cm_write_int_n = '0') else
		(others => 'Z');

	-- I/O Interface (8 bit and 16 bit when enabled)
	io_data_w(7 downto 0) <= host_data_low when io_enab = '1' else (others => '0');

	--########################################################
	-- The below is used for a 16 bit I/O space configuration
	--	io_data_w(15 downto 8) <= host_data_high when (io_write_int_n = '0' and io_enab = '1') else
	--		(others => '0');
	--########################################################

	attribute_memory_array: attribute_memory
	port map(	host_addr		=> host_addr,
					am_read_n		=> am_read_n,
					am_write_n		=> am_write_n,
					we_n				=> we_n,
					am_reset			=> am_reset,
					am_data_r		=> am_data_r,
					io_irq_pending	=> io_irq_pending,
					cm_sts			=> cm_sts,
					io_clk			=> io_clk,
					stschg_n			=> stschg_n,
					io_ireq_route	=> io_ireq_route,
					io_enab			=> io_enab,
					level_pulse_n	=> level_pulse_n,
					soft_reset		=> soft_reset,
					am_data_w		=> am_data_w
				);

end behave;