cf_plus_control.vhd

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

-- cf_plus_control.vhd

-- (c) Copyright 2003 Xilinx, Inc
-- All rights reserved

--
-- Created: 1/10/2003 JRH
--	This code implements the interface of the compact flash CF+ interface

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity cf_plus_control is
  
port(
		-- **** CF+ bus signals ****
		-- inputs
		host_addr		: in	std_logic_vector(10 downto 0);	-- address bus
		ce1_n				: in	std_logic;			
		ce2_n				: in	std_logic;			
		iord_n			: in	std_logic;			
		iowr_n			: in	std_logic;			
		oe_n				: in	std_logic;			
		reg_n				: in	std_logic;			
		reset				: in	std_logic;						
		we_n				: in	std_logic;			
		
		-- outputs
		stschg_n			: out	std_logic;			
		level_pulse_n	: out std_logic;								-- level or pulse mode IRQ from LevelREQ bit in COR
		ireq_n			: out	std_logic;								-- rdy_bsy_n for Memory Mode
		wait_n			: out	std_logic;			

		-- inouts
		host_data_low	: inout	std_logic_vector(7 downto 0);	-- data bus low byte
		host_data_high	: inout	std_logic_vector(7 downto 0);	-- data bus high byte (16 bit data busses only)


		-- **** 28F320J3a Intel StrataFlash Interface ****

		-- inputs
		cm_sts			: in	std_logic;								-- common memory status
		cm_wait			: in	std_logic;								-- common memory status

		-- outputs
		cm_byte_n		: out	std_logic;								-- common memory 16-bit/8-bit select
		cm_addr			: out	std_logic_vector(10 downto 0);	-- common memory address bus
		cm_reset			: out	std_logic;								-- common memory reset

		-- inouts
		cm_read_n		: inout	std_logic;							-- common memory oe
		cm_data			: inout std_logic_vector(15 downto 0);	-- Common Memory word
		cm_ce_n			: inout	std_logic;							-- common memory chip enable
		cm_write_n		: inout	std_logic;							-- common memory we

		-- I/O Interface signals
		-- inputs
		io_clk			: in std_logic;								-- I/O space clock
		io_irq_pending	: in std_logic;								-- for INT bit of CSR
		io_wait_n		: in std_logic;
		io_irq_n			: in	std_logic;
		io_read_valid	: in std_logic;								-- indicates I/O register read data is valid
		--########################################################
		-- Change this vector to (15 downto 0) for 16 bit I/O Space modes
		io_data_r		: in	std_logic_vector(7 downto 0);		-- I/O initerface read data byte		
		--########################################################

		-- outputs
		io_reset			: out std_logic;								-- reset from the CF+ interface
		--########################################################
		-- Change this vector to (15 downto 0) for 16 bit I/O Space modes
		io_data_w		: out	std_logic_vector(7 downto 0);		-- I/O initerface write data byte
		--########################################################
		io_addr			: out std_logic_vector(10 downto 0);	-- host address to I/O space
		io_read_n		: inout	std_logic;			
		io_write_n		: inout	std_logic			
		);

end cf_plus_control;

architecture behave of cf_plus_control is

-- **************************** Constant Declarations ****************************

constant RESET_ACTIVE 		: std_logic := '1';

-- ****************************** Signal Declarations ****************************

-- Attribute Memory Signals
signal	am_reset				: std_logic;
signal	am_read_n			: std_logic;
signal	am_write_n			: std_logic;
signal	am_data_r			: std_logic_vector(7 downto 0);
signal	am_data_w			: std_logic_vector(7 downto 0);
signal	soft_reset			: std_logic;
signal	io_enab				: std_logic;
signal 	io_ireq_route		: std_logic;

-- Common Memory Signals
signal	cm_write_int_n		: std_logic;
signal	cm_address_state	: std_logic;

-- I/O Interface Signals
signal 	io_interrupt_n 	: std_logic;
signal	io_inhibit_cm		: std_logic;

-- Control Signals
signal	card_reset			: std_logic;
signal	eight_even			: std_logic;	-- 8/16-bit mode 	(even byte)
signal	eight_odd			: std_logic;	-- 8-bit mode 		(odd byte)
signal	sixteen_odd			: std_logic;	-- 16-bit mode 	(odd byte only)
signal	sixteen_even_odd	: std_logic;	-- 16-bit mode 	(even & odd byte)

-- **************************** Component Declarations ****************************

component attribute_memory
port(	host_addr		: in	std_logic_vector(10 downto 0);	-- address bus
		am_read_n		: in	std_logic;			
		am_write_n		: in	std_logic;			
		we_n				: in	std_logic;								-- clock input for write operations		
		am_reset			: in	std_logic;			
		am_data_w		: in	std_logic_vector(7 downto 0);		-- control register write data byte
		io_irq_pending	: in  std_logic;								-- for INT bit of CSR
		cm_sts			: in	std_logic;								-- Status of common memory
		io_clk			: in	std_logic;								-- I/O space clock
		stschg_n			: out	std_logic;			
		io_ireq_route	: out std_logic;								-- I/O Enable IREQ Routing
		io_enab			: out std_logic;								-- I/O Space enable from Conf0 bit in COR
		level_pulse_n	: out std_logic;								-- level or pulse mode IRQ from LevelREQ bit in COR
		soft_reset		: out std_logic;								-- soft reset from SRESET bit in COR
		am_data_r		: out	std_logic_vector(7 downto 0)		-- control register read data byte
	);
end component;

begin

	--********************************************************************************
	--*							Attribute Memory Logic												*
	--********************************************************************************
	-- Attribute Memory reset
	am_reset <= '0' when reset = RESET_ACTIVE else '1';	-- intentionally using reset pin
																			-- and not SRESET bit
																			
	--********************************************************************************
	--*								Common Memory Logic												*
	--********************************************************************************
	-- Common Memory address
	cm_memory_address: process(card_reset, io_clk, reg_n, ce1_n, ce2_n, io_inhibit_cm)
	begin
		if card_reset = RESET_ACTIVE then
			cm_addr(10 downto 0) <= (others => 'Z');
			cm_address_state <= '0';
			
		elsif io_clk'event and io_clk = '1' then
		
			if (reg_n = '1'  and (ce1_n = '0' or ce2_n ='0') and io_inhibit_cm = '0') then
				cm_addr(10 downto 1) <= host_addr(10 downto 1);
				cm_address_state <= '1';
			else
				cm_addr(10 downto 1) <= (others => 'Z');
				cm_address_state <= '0';
			end if;
			
			if (reg_n = '1'  and ((ce1_n = '0' and ce2_n ='1') or (ce1_n = '0' and ce2_n ='0')) and io_inhibit_cm = '0') then
				cm_addr(0) <= 	host_addr(0);
			elsif (reg_n = '1'  and (ce1_n = '1' and ce2_n ='0') and io_inhibit_cm = '0') then
				cm_addr(0) <= 	'1';
			else
				cm_addr(0) <= 	'Z';
			end if;
			
		end if;
	end process;
	
	
	-- Common Memory chip enable
	cm_chip_enable: process(card_reset, io_clk, reg_n, ce1_n, ce2_n, cm_address_state)
	begin
		if card_reset = RESET_ACTIVE then
			cm_ce_n <= '1';
		elsif io_clk'event and io_clk = '1' then
			if (reg_n = '1' and (ce1_n = '0' or ce2_n ='0') and cm_address_state = '1') then
				cm_ce_n <= '0';
			else
				cm_ce_n <= '1';
			end if;
		end if;
	end process;
	
	
	-- Common Memory byte mode select
	cm_byte_mode: process(card_reset, io_clk, ce1_n, ce2_n, reg_n, cm_address_state)
	begin
		if card_reset = RESET_ACTIVE then
			cm_byte_n <= '1';
			
		elsif io_clk'event and io_clk = '1' then
			if ((ce1_n = '0' xor ce2_n = '0') and reg_n = '1' and cm_address_state = '1') then
				cm_byte_n <= '0';
				
			else
				cm_byte_n <= '1';
			
			end if;
		end if;
	end process;
				
	-- Common Memory status
	wait_n <= cm_wait when reg_n = '1' else 		-- Remove this cm_wait logic if external memory does not support bus cycle extending signals.
				io_wait_n when (iord_n = '0' or iowr_n = '0') else
				'1';
	
	-- Common Memory reset
	cm_reset <= '0' when card_reset = RESET_ACTIVE else '1';
	

	--********************************************************************************
	--*									I/O Space Logic												*
	--********************************************************************************
	-- I/O Space address
	io_addr <= host_addr when io_enab = '1' else (others => '0');
	
	-- I/O Reset
	io_reset <= '0' when card_reset = RESET_ACTIVE else '1';

	
	io_interrupt_n <= io_irq_n when io_ireq_route = '1' else '1';
	
	--********************************************************************************
	--*			 					CF Card Control Logic											*
	--********************************************************************************
	
	--************************ ireq_n and ready/busy_n logic *************************
	ireq_n <=	cm_sts when (io_enab = '0' and card_reset = not(RESET_ACTIVE)) else				-- card not configured as I/O.  Pin acts as Rdy/Bsy_n
					io_interrupt_n when (io_enab = '1' and card_reset = not(RESET_ACTIVE)) else	-- card configured as I/O.  Pin acts as IRQ_n
					'0'; 																									-- reset condition exists