attribute_memory.vhd

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

-- attribute_memory.vhd

-- (c) Copyright 2003 Xilinx, Inc
-- All rights reserved

--
-- Created: 2/7/2003 JRH
--	This code implements the attribute memory

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity attribute_memory is
  
port(	
		-- inputs
		host_addr		: in	std_logic_vector(10 downto 0);	-- address bus
		am_read_n		: in	std_logic;			
		am_write_n		: in	std_logic;			
		we_n				: in	std_logic;			
		am_reset			: in	std_logic;			
		am_data_w		: in	std_logic_vector(7 downto 0);		-- control register write data byte
		io_irq_pending	: in  std_logic;								-- for INT bit of CSR
		cm_sts			: in	std_logic;								-- Status of common memory
		io_clk			: in	std_logic;								-- I/O space clock

		-- outputs
		stschg_n			: out	std_logic;			
		io_ireq_route	: out std_logic;								-- I/O Enable IREQ Routing
		io_enab			: out std_logic;								-- I/O Space enable from Conf0 bit in COR
		level_pulse_n	: out std_logic;								-- level or pulse mode IRQ from LevelREQ bit in COR
		soft_reset		: out std_logic;								-- soft reset from SRESET bit in COR
		am_data_r		: out	std_logic_vector(7 downto 0)		-- control register read data byte
		);	

end attribute_memory;

architecture behave of attribute_memory is

-- **************************** Constant Declarations ****************************

constant BASE					: std_logic_vector(6 downto 0) := "0100000";	-- Configuration Registers Base Address (200h) (last 4 bits ommitted for adders)
constant COR_ADDR				: std_logic_vector(3 downto 0) := "0000";	-- Configuration Option Register Address Adder (+0h)
constant CSR_ADDR				: std_logic_vector(3 downto 0) := "0010";	-- Card Configuration and Staus Register Address Adder (+2h)
constant PRR_ADDR				: std_logic_vector(3 downto 0) := "0100";	-- Pin Replacement Register Address Adder (+4h)
--constant SCR_ADDR			: std_logic_vector(3 downto 0) := "0110";	-- Socket and Copy Register Address Adder (+6h)

-- ****************************** Signal Declarations ****************************

-- Configuration Option Register (COR)
signal	SRESET				: std_logic;
signal	LevlREQ				: std_logic;
signal	Conf					: std_logic_vector (5 downto 0);
	
-- Card Configuration and Staus Register (CSR)
signal	Changed				: std_logic;
signal	SigChg				: std_logic;
--signal	IOis8					: std_logic;	-- Not used in this implementation of the CF+ interface
--signal	XE_n					: std_logic;	-- Not used in this implementation of the CF+ interface
--signal	Audio					: std_logic;	-- Not used in this implementation of the CF+ interface
--signal	PwrDwn				: std_logic;	-- Not used in this implementation of the CF+ interface
signal	Int					: std_logic;

-- Pin Replacement Register (PRR)
signal	CRdy_Bsy_n			: std_logic;
signal	Host_CRdy_Bsy_n	: std_logic;	-- CRdy_Bsy_n bit set by host
--signal	CWProt				: std_logic;	-- Not used for CF+ interface
signal	Rdy_Bsy_n			: std_logic;
signal	MRdy_Bsy_n			: std_logic;	-- Masked Rdy_Bsy_n
--signal	WProt					: std_logic;	-- Not used for CF+ interface and is always zero

-- Socket and Copy Register (SCR)
--signal	Drive					: std_logic;	-- Not used in this implementation of the CF+ interface

-- CIS signals
signal	cis_addr				: std_logic_vector(10 downto 0);
signal	cis_data				: std_logic_vector(7 downto 0);


-- **************************** Component Declarations ****************************
component cis
port(	
		cis_addr	: in	std_logic_vector(10 downto 0);	-- address bus
		cis_data	: out	std_logic_vector(7 downto 0)	-- data byte
		);
end component;

begin

	cis_addr <= host_addr;
	
	--	***************** Configuration Option Register (COR) Functionality ******************
	-- SRESET bit
	soft_reset <= SRESET;
	
	-- LevlREQ bit
	level_pulse_n <= LevlREQ;
	
	-- I/O enable bit
	io_enab <= Conf(0);
	
	-- I/O Ebable IREQ# Routing
	io_ireq_route <= Conf(2);
	
	--	************** Card Configuration and Staus Register (CSR) Functionality *************
	-- Int bit (read only)
	Int <= io_irq_pending when (am_reset = '1' and SRESET = '0') else '0';
	
	-- Changed bit (read only)
	stschg_n <= not(Changed) when (SigChg = '1' and Conf(0) = '1') else '1';
	
	Changed <= CRdy_Bsy_n when (am_reset = '1' and SRESET = '0') else '0';
	
	--	******************** CPin Replacement Register (PRR) Functionality ********************
	-- Rdy/Bsy_n bit
	Rdy_Bsy_n <= cm_sts when (am_reset = '1' and SRESET = '0') else '0';		-- reflects common memory status.  Reset to zero indicating a Busy condition

	-- CRdy/Bsy_n bit
	Change_Ready_Busy: process(am_reset, SRESET, io_clk, Rdy_Bsy_n, MRdy_Bsy_n)
	begin
		if (am_reset = '0' or SRESET = '1') then
			CRdy_Bsy_n <= '0';
			
		elsif(io_clk'event and io_clk = '1') then
			if (MRdy_Bsy_n = '0' and Rdy_Bsy_n = '0') then
				CRdy_Bsy_n <= '1';
			
			elsif (MRdy_Bsy_n = '0' and Rdy_Bsy_n = '1') then
				CRdy_Bsy_n <= CRdy_Bsy_n;
				
			elsif MRdy_Bsy_n = '1' then
				CRdy_Bsy_n <= Host_CRdy_Bsy_n;

			else
				CRdy_Bsy_n <= CRdy_Bsy_n;
			
			end if;
		end if;
		
	end process;


	--*********************** Read from Status and Control Registers *************************
	read_attribute_memory: process(host_addr, am_read_n, am_write_n, SRESET, LevlREQ, Conf, Changed, SigChg, Int, CRdy_Bsy_n, Rdy_Bsy_n, cis_data)
	begin
		if am_read_n = '0' then
			-- Configuration Option Register (COR)
			if host_addr = (BASE & COR_ADDR) then
				am_data_r <= SRESET & LevlREQ & Conf;

			-- Card Configuration and Staus Register (CSR)
			elsif host_addr = (BASE & CSR_ADDR) then
				am_data_r <= Changed & SigChg & '1' & '0' & '0' & '0' & Int & '0';
				-- IOis8 defaults to a '1' to indicate 8 bit I/O mode for this CF+ implementation
				
				-- XE_n defaults to a '0' to indicate power level 1 commands are enabled, 
				--	but this implementation does not support power level commands.  CF cards default
				-- to a '1' for XE_n otherwise.
				
				-- Audio  defaults to a '0' since audio is not supported in this CF+ implementation.
				
				-- PwrDwn defaults to a '0' to indicate active power mode.  This CF+ implementation
				-- does not support power down modes

			-- Pin Replacement Register (PRR)
			elsif host_addr = (BASE & PRR_ADDR) then
				am_data_r <= '0' & '0' & CRdy_Bsy_n & '0' & '1' & '1' & Rdy_Bsy_n & '0';

--			-- Socket and Copy Register (SCR)
--			elsif host_addr = (BASE & PRR_ADDR) then
--				am_data_r <= '0' & '0' & '0' & Drive & '0' & '0' & '0' & '0';
	
			-- Card Information Structure (CIS)
			else
				am_data_r <= cis_data;
			end if;
		elsif (am_read_n = '1' and am_write_n = '1') then
			am_data_r <= (others => '0');
		end if;
			
	end process;

	--*********************** Write to Status and Control Registers *************************
	write_attribute_memory: process(host_addr, am_write_n, we_n, am_reset)
	begin
		if am_reset = '0' then

		-- Configuration Option Register (COR)
			SRESET				<= '0';
			LevlREQ				<= '0';
			Conf					<= (others => '0');

			-- Card Configuration and Staus Register (CSR)
			SigChg				<= '0';

			-- Pin Replacement Register (PRR)
			Host_CRdy_Bsy_n	<= '0';
			MRdy_Bsy_n			<= '0';

--			-- Socket and Copy Register (SCR)
--			Drive					<= '0';
		
		elsif we_n'event and we_n = '1' then
			
			if am_write_n = '0' then
				if am_data_w(7) = '1' and host_addr = (BASE & COR_ADDR) then		-- resets all bits in Configuration Registers except SRESET bit in COR

					-- Configuration Option Register (COR)
						SRESET				<= '1';
						LevlREQ				<= '0';
						Conf					<= (others => '0');

					-- Card Configuration and Staus Register (CSR)
						SigChg				<= '0';

					-- Pin Replacement Register (PRR)
						Host_CRdy_Bsy_n	<= '0';
						MRdy_Bsy_n			<= '0';

	--				-- Socket and Copy Register (SCR)
	--					Drive					<= '0';
					

				else
				
					-- Configuration Option Register (COR)
					if host_addr = (BASE & COR_ADDR) then
						SRESET				<= am_data_w(7);
						LevlREQ				<= am_data_w(6);
						Conf					<= am_data_w(5 downto 0);
	
					-- Card Configuration and Staus Register (CSR)
					elsif host_addr = (BASE & CSR_ADDR) then
						SigChg				<= am_data_w(6);

					-- Pin Replacement Register (PRR)
					elsif host_addr = (BASE & PRR_ADDR) then
						Host_CRdy_Bsy_n	<= am_data_w(5);
						MRdy_Bsy_n			<= am_data_w(1);

	--				-- Socket and Copy Register (SCR)
	--				elsif host_addr = (BASE & PRR_ADDR) then
	--					Drive					<= am_data_w(4);

					-- Card Information Structure (CIS)
					-- write to CIS is an invalid operation
					
					end if;

				end if;
			end if;
		end if;
			
	end process;

	cis_data_array: cis
	port map(cis_addr	=> cis_addr,
				cis_data	=> cis_data
				);
	
end behave;