readme.txt

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

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Readme File for CF+ Customer Pack

(c) Copyright 2003 Xilinx, Inc
All rights reserved

Created: 6/27/2003 JRH

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DISCLAIMER
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THIS DESIGN IS PROVIDED TO YOU "AS IS". XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR 
CONDITIONS, EXPRESS, IMPLIED,  STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY 
IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR 
PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an 
example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this 
Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in 
the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the 
results of the use of the Design in terms of correctness, accuracy, reliability or otherwise. 

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File Contents
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This zip file contains the following folders:

\work				- XST and ModelSim compiled VHDL files

-- VHDL Source Files:
	attribute_memory.vhd 	- contains attribute memory functionality
	cf_plus.vhd		- top level file
	cf_plus_control.vhd 	- control logic for the CF+ interface
	cis.vhd			- Card Information Structure ROM
	dsp_interface.vhd	- interface to ADI DSP ADSP-218xN
	upcnt6.vhd		- 6-bit up counter
	timesim.vhd		- XST compiled version of attribute_memory.vhd, cf_plus.vhd,
					cf_plus_control.vhd, cis.vhd, dsp_interface, and 
					upcnt6.vhd which contains the timing delay data for 
					the XC2C256-7-TQ144 device to which this CF+ interface 
					design was targeted.
				
-- VHDL Testbench Files:	
	testbench.vhd		- VHDL testbench for functional and post route simulation
	
	
-- ModelSim DO files:	
	test_func.do		- functional simulation script file that compiles 
					attribute_memory.vhd, cf_plus.vhd, cf_plus_control.vhd, 
					cis.vhd, dsp_interface, and upcnt6.vhd. Then calls 
					wave_func.do.  This file also compiles the Intel
					StrataFlash memory module written in VHDL.
	wave_func.do		- configures wave window for functional simulation
	test_post.do		- post route timing simulation script file that compiles 
					timesim.vhd. Then calls wave_post.do.  This file also 
					compiles the Intel StrataFlash memory module written
					in VHDL.
	wave_post.do		- configures wave window for post route simulation

-- Other Files:	
	initfile.dat		- data that is used to initialize the Intel StrataFlash memory
	cf_plus.cxt		- XPower input file containing the structure of the post fit design
	cf_plus.vcd		- XPower simulation file containing activity rates of all top level nets
	cf_plus.jed		- JEDEC file containing the post route design to be programmed into
					a XC2C256-7-TQ144 device.
	cf_plus.rpt		- contains the post fit report of the design
	cf_plus.ucf		- device constraints file
	cf_plus.npl		- project file for XST
	readme.txt		- this file
	readme.doc		- this file in Microsoft Word format
	
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Design Notes
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This design also requires the VHDL model of the Intel StrataFlash 28F320J3 configured for 32MB which can be 
downloaded from the Intel web site at http://appzone.intel.com/toolcatalog/listtools.asp?pid=5319&cid=683&pfamily=
This VHDL file must also be configured to initialize using the initfile.dat, included in this zip file.

The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices 
ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification. Complete 
documentation for the design can be found in XAPP398 available for download from the Xilinx website.

All of the register addresses are defined as constants in the VHDL source files and can be easily customized for customer 
use. 

Please note that this design has been verified through simulations, but not on actual hardware.

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Technical Support
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Technical support for this design and any other CoolRunner CPLD issues can be obtained as follows:

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