cf_plus.vhd

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

-- cf_plus.vhd

-- (c) Copyright 2003 Xilinx, Inc
-- All rights reserved

--
-- Created: 2/25/2003 JRH
--
-- This code implements the control of the CF+ interface with a ADSP-281xN type I/O Space
--	interface. The CF+ control logic is done in the component cf_plus_control and the
--	I/O interface is implemented in the component dsp_interface. This file does not contain
--	any logic descriptions, it simply instantiates the two components and hooks them together.
--

library IEEE;
use IEEE.std_logic_1164.all;

entity cf_plus is 
	port (
			-- **** CF+ bus signals ****
			-- inputs
			host_addr		: in	std_logic_vector(10 downto 0);	-- address bus
			ce1_n				: in	std_logic;			
			ce2_n				: in	std_logic;			
			iord_n			: in	std_logic;			
			iowr_n			: in	std_logic;			
			oe_n				: in	std_logic;			
			reg_n				: in	std_logic;			
			reset				: in	std_logic;						
			we_n				: in	std_logic;			
			
			-- outputs
			stschg_n			: out	std_logic;			
			inpack_n			: out	std_logic;			
			ireq_n			: out	std_logic;								-- rdy_bsy_n for Memory Mode
			wait_n			: out	std_logic;			

			-- inouts
			host_data_low	: inout	std_logic_vector(7 downto 0);	-- data bus low byte
			host_data_high	: inout	std_logic_vector(7 downto 0);	-- data bus high byte (16 bit data busses only)


			-- **** 28F320J3a Intel StrataFlash Interface ****
			-- inputs
			cm_sts			: in	std_logic;								-- common memory status
			cm_wait			: in	std_logic;								-- common memory status

			-- outputs
			cm_byte_n		: out	std_logic;								-- common memory 16-bit/8-bit select
			cm_addr			: out	std_logic_vector(10 downto 0);	-- common memory address bus
			cm_reset			: out	std_logic;								-- common memory reset

			-- inouts
			cm_read_n		: inout	std_logic;							-- common memory oe
			cm_data			: inout std_logic_vector(15 downto 0);	-- Common Memory word
			cm_ce_n			: inout	std_logic;							-- common memory chip enable
			cm_write_n		: inout	std_logic;							-- common memory we

			-- **** ADSP-281xN I/O space interface ****
			-- inputs
			dsp_clk			: in std_logic;								-- clkout of DSP
			dsp_addr			: in std_logic_vector (10 downto 0);
			dsp_ioms_n		: in std_logic; 								-- I/O Memory Select, active low	
			dsp_rd_n 		: in std_logic; 								-- Read strobe, active low
			dsp_wr_n 		: in std_logic; 								-- Read strobe, active low

			-- inouts
			dsp_data			: inout std_logic_vector (7 downto 0)
			
			);
end cf_plus;
		
architecture behave of cf_plus is

-- **************************** Component Declarations ****************************

-- Define the CF+ Control logic
component cf_plus_control 
	port(
			-- CF+ bus signals
			-- inputs
			host_addr		: in	std_logic_vector(10 downto 0);	-- address bus
			ce1_n				: in	std_logic;			
			ce2_n				: in	std_logic;			
			iord_n			: in	std_logic;			
			iowr_n			: in	std_logic;			
			oe_n				: in	std_logic;			
			reg_n				: in	std_logic;			
			reset				: in	std_logic;						
			we_n				: in	std_logic;			

			-- outputs
			stschg_n			: out	std_logic;			
			level_pulse_n	: out std_logic;								-- level or pulse mode IRQ from LevelREQ bit in COR
			ireq_n			: out	std_logic;								-- rdy_bsy_n for Memory Mode
			wait_n			: out	std_logic;			

			-- inouts
			host_data_low	: inout	std_logic_vector(7 downto 0);	-- data bus low byte
			host_data_high	: inout	std_logic_vector(7 downto 0);	-- data bus high byte (16 bit data busses only)


			-- 28F320J3a Intel StrataFlash Interface

			-- inputs
			cm_sts			: in	std_logic;								-- common memory status
			cm_wait			: in	std_logic;								-- common memory status

			-- outputs
			cm_byte_n		: out	std_logic;								-- common memory 16-bit/8-bit select
			cm_addr			: out	std_logic_vector(10 downto 0);	-- common memory address bus
			cm_reset			: out	std_logic;								-- common memory reset

			-- inouts
			cm_read_n		: inout	std_logic;							-- common memory oe
			cm_data			: inout std_logic_vector(15 downto 0);	-- Common Memory word
			cm_ce_n			: inout	std_logic;							-- common memory chip enable
			cm_write_n		: inout	std_logic;							-- common memory we

			-- I/O Interface signals
			-- inputs
			io_clk			: in std_logic;								-- I/O space clock
			io_irq_pending	: in std_logic;								-- for INT bit of CSR
			io_wait_n		: in	std_logic;
			io_irq_n			: in	std_logic;
			io_read_valid	: in std_logic;								-- indicates I/O register read data is valid
			--########################################################
			-- Change this vector to (15 downto 0) for 16 bit I/O Space modes
			io_data_r		: in	std_logic_vector(7 downto 0);		-- I/O initerface read data byte		
			--########################################################

			-- outputs
			io_reset			: out std_logic;								-- reset from the CF+ interface
			--########################################################
			-- Change this vector to (15 downto 0) for 16 bit I/O Space modes
			io_data_w		: out	std_logic_vector(7 downto 0);		-- I/O initerface write data byte
			--########################################################
			io_addr			: out std_logic_vector(10 downto 0);		-- host address to I/O space

			-- inouts
			io_read_n		: inout	std_logic;			
			io_write_n		: inout	std_logic			
			);

end component;

-- Define the I/O interface
component dsp_interface 
	port(
			-- **** ADSP-281xN I/O space interface ****
			-- inputs
			dsp_clk			: in std_logic;								-- clkout of DSP
			dsp_addr			: in std_logic_vector (10 downto 0);
			dsp_ioms_n		: in std_logic; 								-- I/O Memory Select, active low	
			dsp_rd_n 		: in std_logic; 								-- Read strobe, active low
			dsp_wr_n 		: in std_logic; 								-- Read strobe, active low

			-- inouts
			dsp_data			: inout std_logic_vector (7 downto 0);
			
			-- **** I/O Interface internal control signals ****
			-- inputs
			level_pulse_n	: in std_logic;								-- level or pulse mode IRQ from LevelREQ bit in COR
			io_reset			: in std_logic;								-- reset from the CF+ interface
			--########################################################
			-- Change this vector to (15 downto 0) for 16 bit I/O Space modes
			io_data_w		: in std_logic_vector(7 downto 0);		-- I/O initerface write data byte
			--########################################################
			io_addr			: in std_logic_vector(10 downto 0);		-- host address to I/O space
			io_read_n		: in std_logic;			
			io_write_n		: in std_logic;
			iowr_n			: in std_logic;

			-- outputs
			io_irq_pending	: out std_logic;								-- for INT bit of CSR
			io_irq_n			: out std_logic;								-- new data has been written to any register by the DSP
			io_wait_n		: out std_logic;
			inpack_n			: out std_logic;
			io_read_valid	: out std_logic;								-- indicates I/O register read data is valid
			--########################################################
			-- Change this vector to (15 downto 0) for 16 bit I/O Space modes
			io_data_r		: out	std_logic_vector(7 downto 0)		-- I/O initerface read data byte		
			--########################################################
			);
end component;

-- ****************************** Signal Declarations ****************************

-- CF+ bus signals
signal io_read_valid		: std_logic;
signal io_wait_n			: std_logic;
signal io_irq_n			: std_logic;
signal level_pulse_n		: std_logic;
signal io_irq_pending	: std_logic;

--########################################################
-- Change this vector to (15 downto 0) for 16 bit I/O Space modes
signal io_data_r			: std_logic_vector(7 downto 0);
--########################################################

signal io_reset			: std_logic;
signal io_read_n			: std_logic;			
signal io_write_n			: std_logic;			

--########################################################
-- Change this vector to (15 downto 0) for 16 bit I/O Space modes
signal io_data_w			: std_logic_vector(7 downto 0);
--########################################################

signal io_addr				: std_logic_vector(10 downto 0);


begin

-- ****************************** Component Instantiations ****************************
 
	cf_plus_logic: cf_plus_control
	port map (
					host_addr		=> host_addr,
					ce1_n				=> ce1_n,
					ce2_n				=> ce2_n,
					iord_n			=> iord_n,
					iowr_n			=> iowr_n,
					oe_n				=> oe_n,
					reg_n				=> reg_n,
					reset				=> reset,
					we_n				=> we_n,
					stschg_n			=> stschg_n,
					level_pulse_n	=> level_pulse_n,
					ireq_n			=> ireq_n,
					wait_n			=> wait_n,
					host_data_low	=> host_data_low,
					host_data_high	=> host_data_high,
					cm_sts			=> cm_sts,
					cm_wait			=> cm_wait,
					cm_byte_n		=> cm_byte_n,
					cm_addr			=> cm_addr,
					cm_reset			=> cm_reset,
					cm_read_n		=> cm_read_n,
					cm_data			=> cm_data,
					cm_ce_n			=> cm_ce_n,
					cm_write_n		=> cm_write_n,
					io_clk			=> dsp_clk,
					io_irq_pending	=> io_irq_pending,
					io_wait_n		=> io_wait_n,
					io_irq_n			=> io_irq_n,
					io_read_valid	=> io_read_valid,
					io_data_r		=> io_data_r,
					io_reset			=> io_reset,
					io_data_w		=> io_data_w,
					io_addr			=> io_addr,
					io_read_n		=> io_read_n,
					io_write_n		=> io_write_n
				);

	io_interface_logic: dsp_interface 
	port map(
					dsp_clk			=> dsp_clk,
					dsp_addr			=> dsp_addr,
					dsp_ioms_n		=> dsp_ioms_n,
					dsp_rd_n			=> dsp_rd_n,
					dsp_wr_n			=> dsp_wr_n,
					dsp_data			=> dsp_data,
					level_pulse_n	=> level_pulse_n,
					io_reset			=> io_reset,
					io_data_w		=> io_data_w,
					io_addr			=> io_addr,
					io_read_n		=> io_read_n,
					io_write_n		=> io_write_n,
					iowr_n			=> iowr_n,
					io_irq_pending	=> io_irq_pending,
					io_irq_n			=> io_irq_n,
					io_wait_n		=> io_wait_n,
					inpack_n			=> inpack_n,
					io_read_valid	=> io_read_valid,
					io_data_r		=> io_data_r
				);
		

end behave;