dff_2.vhd

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

library ieee;
use ieee.std_logic_1164.all;
entity dff_2 is
port(d:in std_logic;
     clk:in std_logic;
     q:out std_logic);
end dff_2;

architecture rtl of dff_2 is
begin
  dff_process:process(clk)
  begin
    if (clk'event and clk='1') then
    q<=d;
    end if;
  end process dff_process;
end rtl;