ads7844.sim.rpt

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

; Complete 1/0-Value Coverage                                                                              ;
+-------------------------------------------+-------------------------------------------+------------------+
; Node Name                                 ; Output Port Name                          ; Output Port Type ;
+-------------------------------------------+-------------------------------------------+------------------+
; |ads7844|to_ad:inst4|74165b:inst|94       ; |ads7844|to_ad:inst4|74165b:inst|94       ; regout           ;
; |ads7844|cs_pulse:inst5|inst6             ; |ads7844|cs_pulse:inst5|inst6             ; regout           ;
; |ads7844|addr_1:inst1|current_state.s0    ; |ads7844|addr_1:inst1|current_state.s0    ; regout           ;
; |ads7844|addr_1:inst1|current_state.s2    ; |ads7844|addr_1:inst1|current_state.s2    ; regout           ;
; |ads7844|addr_1:inst1|current_state.s6    ; |ads7844|addr_1:inst1|current_state.s6    ; regout           ;
; |ads7844|addr_1:inst1|WideOr2~11          ; |ads7844|addr_1:inst1|WideOr2~11          ; combout          ;
; |ads7844|addr_1:inst1|WideOr2~11          ; |ads7844|addr_1:inst1|current_state.s4    ; regout           ;
; |ads7844|addr_1:inst1|current_state.s5    ; |ads7844|addr_1:inst1|current_state.s5    ; regout           ;
; |ads7844|addr_1:inst1|WideOr0~18          ; |ads7844|addr_1:inst1|WideOr0~18          ; combout          ;
; |ads7844|addr_1:inst1|current_state.s3    ; |ads7844|addr_1:inst1|current_state.s3    ; regout           ;
; |ads7844|addr_1:inst1|WideOr1~12          ; |ads7844|addr_1:inst1|WideOr1~12          ; combout          ;
; |ads7844|fq_cs:inst3|q[2]                 ; |ads7844|fq_cs:inst3|q[2]~55              ; cout0            ;
; |ads7844|fq_cs:inst3|q[2]                 ; |ads7844|fq_cs:inst3|q[2]~55COUT1_76      ; cout1            ;
; |ads7844|fq_cs:inst3|q[0]                 ; |ads7844|fq_cs:inst3|q[0]~56              ; cout0            ;
; |ads7844|fq_cs:inst3|q[0]                 ; |ads7844|fq_cs:inst3|q[0]~56COUT1_72      ; cout1            ;
; |ads7844|fq_cs:inst3|q[1]                 ; |ads7844|fq_cs:inst3|q[1]~57              ; cout0            ;
; |ads7844|fq_cs:inst3|q[1]                 ; |ads7844|fq_cs:inst3|q[1]~57COUT1_74      ; cout1            ;
; |ads7844|fq_cs:inst3|q[3]                 ; |ads7844|fq_cs:inst3|q[3]~58              ; cout0            ;
; |ads7844|fq_cs:inst3|q[3]                 ; |ads7844|fq_cs:inst3|q[3]~58COUT1_78      ; cout1            ;
; |ads7844|fq_cs:inst3|LessThan0~57         ; |ads7844|fq_cs:inst3|LessThan0~57         ; combout          ;
; |ads7844|fq_cs:inst3|LessThan0~58         ; |ads7844|fq_cs:inst3|LessThan0~58         ; combout          ;
; |ads7844|fq_cs:inst3|LessThan0~58         ; |ads7844|fq_cs:inst3|cs~reg0              ; regout           ;
; |ads7844|fq:inst|Equal0~35                ; |ads7844|fq:inst|Equal0~35                ; combout          ;
; |ads7844|to_ad:inst4|74165b:inst|95       ; |ads7844|to_ad:inst4|74165b:inst|95       ; regout           ;
; |ads7844|to_ad:inst4|74165b:inst|102      ; |ads7844|fq_cs:inst3|dff_2:u2|q           ; regout           ;
; |ads7844|to_ad:inst4|74165b:inst|103      ; |ads7844|to_ad:inst4|74165b:inst|103      ; combout          ;
; |ads7844|fq_cs:inst3|dff_2:u1|q           ; |ads7844|fq_cs:inst3|dff_2:u1|q           ; regout           ;
; |ads7844|cs_pulse:inst5|inst3             ; |ads7844|cs_pulse:inst5|inst3             ; regout           ;
; |ads7844|addr_1:inst1|current_state.s1    ; |ads7844|addr_1:inst1|current_state.s1    ; regout           ;
; |ads7844|to_ad:inst4|74165b:inst|96       ; |ads7844|to_ad:inst4|74165b:inst|96       ; regout           ;
; |ads7844|to_ad:inst4|74165b:inst|105      ; |ads7844|to_ad:inst4|74165b:inst|105      ; combout          ;
; |ads7844|to_ad:inst4|74165b:inst|104      ; |ads7844|to_ad:inst4|74165b:inst|104      ; combout          ;
; |ads7844|cs_pulse:inst5|cs_wide:inst|co   ; |ads7844|cs_pulse:inst5|cs_wide:inst|co   ; regout           ;
; |ads7844|to_ad:inst4|74165b:inst|97       ; |ads7844|to_ad:inst4|74165b:inst|97       ; regout           ;
; |ads7844|to_ad:inst4|74165b:inst|106      ; |ads7844|to_ad:inst4|74165b:inst|106      ; combout          ;
; |ads7844|to_ad:inst4|74165b:inst|107      ; |ads7844|to_ad:inst4|74165b:inst|107      ; combout          ;
; |ads7844|cs_pulse:inst5|cs_wide:inst|q[1] ; |ads7844|cs_pulse:inst5|cs_wide:inst|q[1] ; regout           ;
; |ads7844|to_ad:inst4|74165b:inst|98       ; |ads7844|to_ad:inst4|74165b:inst|98       ; regout           ;
; |ads7844|to_ad:inst4|74165b:inst|109      ; |ads7844|to_ad:inst4|74165b:inst|109      ; combout          ;
; |ads7844|to_ad:inst4|74165b:inst|108      ; |ads7844|to_ad:inst4|74165b:inst|108      ; combout          ;
; |ads7844|cs_pulse:inst5|cs_wide:inst|q[0] ; |ads7844|cs_pulse:inst5|cs_wide:inst|q[0] ; regout           ;
; |ads7844|to_ad:inst4|74165b:inst|99       ; |ads7844|to_ad:inst4|74165b:inst|99       ; regout           ;
; |ads7844|cs_all                           ; |ads7844|cs_all                           ; combout          ;
; |ads7844|clk                              ; |ads7844|clk                              ; combout          ;
; |ads7844|cs                               ; |ads7844|cs                               ; padio            ;
; |ads7844|clk1                             ; |ads7844|clk1                             ; padio            ;
; |ads7844|di                               ; |ads7844|di                               ; padio            ;
; |ads7844|stld                             ; |ads7844|stld                             ; padio            ;
; |ads7844|cs_ad                            ; |ads7844|cs_ad                            ; padio            ;
; |ads7844|control_word[7]                  ; |ads7844|control_word[7]                  ; padio            ;
; |ads7844|control_word[6]                  ; |ads7844|control_word[6]                  ; padio            ;
; |ads7844|control_word[5]                  ; |ads7844|control_word[5]                  ; padio            ;
; |ads7844|control_word[4]                  ; |ads7844|control_word[4]                  ; padio            ;
; |ads7844|control_word[2]                  ; |ads7844|control_word[2]                  ; padio            ;
; |ads7844|addr[3]                          ; |ads7844|addr[3]                          ; padio            ;
; |ads7844|addr[2]                          ; |ads7844|addr[2]                          ; padio            ;
; |ads7844|addr[1]                          ; |ads7844|addr[1]                          ; padio            ;
; |ads7844|addr[0]                          ; |ads7844|addr[0]                          ; padio            ;
+-------------------------------------------+-------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                                                               ;
+------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                        ; Output Port Name                                                                                                 ; Output Port Type ;
+------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+------------------+
; |ads7844|addr_1:inst1|WideOr0~18                                                                                 ; |ads7844|addr_1:inst1|current_state.s8                                                                           ; regout           ;
; |ads7844|addr_1:inst1|WideOr1~12                                                                                 ; |ads7844|addr_1:inst1|current_state.s7                                                                           ; regout           ;
; |ads7844|fq:inst|counter[2]                                                                                      ; |ads7844|fq:inst|counter[2]                                                                                      ; regout           ;
; |ads7844|fq:inst|counter[3]                                                                                      ; |ads7844|fq:inst|counter[3]                                                                                      ; regout           ;
; |ads7844|to_ad:inst4|74165b:inst|102                                                                             ; |ads7844|to_ad:inst4|74165b:inst|102                                                                             ; combout          ;
; |ads7844|d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[15] ; |ads7844|d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[15] ; portbdataout0    ;
; |ads7844|d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[15] ; |ads7844|d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[15] ; portbdataout1    ;
; |ads7844|d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[15] ; |ads7844|d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[13] ; portbdataout2    ;
; |ads7844|d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[15] ; |ads7844|d_latch:inst6|altsyncram0:inst26|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[13] ; portbdataout3    ;
; |ads7844|d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[15] ; |ads7844|d_latch:inst6|altsyncram0:inst33|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[13] ; portbdataout4    ;
; |ads7844|d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[15] ; |ads7844|d_latch:inst6|altsyncram0:inst29|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[13] ; portbdataout5    ;
; |ads7844|d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[15] ; |ads7844|d_latch:inst6|altsyncram0:inst31|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[12] ; portbdataout6    ;
; |ads7844|d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[15] ; |ads7844|d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[12] ; portbdataout7    ;
; |ads7844|d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[15] ; |ads7844|d_latch:inst6|altsyncram0:inst29|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[12] ; portbdataout8    ;