ads7844.sim.rpt

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

Simulator report for ads7844
Fri Aug 10 22:19:56 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. |ads7844|d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ALTSYNCRAM
  6. |ads7844|d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ALTSYNCRAM
  7. |ads7844|d_latch:inst6|altsyncram0:inst30|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ALTSYNCRAM
  8. |ads7844|d_latch:inst6|altsyncram0:inst33|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ALTSYNCRAM
  9. |ads7844|d_latch:inst6|altsyncram0:inst26|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ALTSYNCRAM
 10. |ads7844|d_latch:inst6|altsyncram0:inst29|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ALTSYNCRAM
 11. |ads7844|d_latch:inst6|altsyncram0:inst28|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ALTSYNCRAM
 12. |ads7844|d_latch:inst6|altsyncram0:inst31|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ALTSYNCRAM
 13. Coverage Summary
 14. Complete 1/0-Value Coverage
 15. Missing 1-Value Coverage
 16. Missing 0-Value Coverage
 17. Simulator INI Usage
 18. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 100.0 us     ;
; Simulation Netlist Size     ; 215 nodes    ;
; Simulation Coverage         ;      17.31 % ;
; Total Number of Transitions ; 7439         ;
; Simulation Breakpoints      ; 0            ;
; Family                      ; Cyclone      ;
; Device                      ; EP1C6Q240C6  ;
+-----------------------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings                                                                                                      ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Option                                                                                     ; Setting    ; Default Value ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Simulation mode                                                                            ; Timing     ; Timing        ;
; Start time                                                                                 ; 0 ns       ; 0 ns          ;
; Add pins automatically to simulation output waveforms                                      ; On         ; On            ;
; Check outputs                                                                              ; Off        ; Off           ;
; Report simulation coverage                                                                 ; On         ; On            ;
; Display complete 1/0 value coverage report                                                 ; On         ; On            ;
; Display missing 1-value coverage report                                                    ; On         ; On            ;
; Display missing 0-value coverage report                                                    ; On         ; On            ;
; Detect setup and hold time violations                                                      ; Off        ; Off           ;
; Detect glitches                                                                            ; Off        ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;