ads7844.hif

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

d_latch:inst6|altsyncram0:inst32
d_latch:inst6|altsyncram0:inst29
d_latch:inst6|altsyncram0:inst30
d_latch:inst6|altsyncram0:inst26
d_latch:inst6|altsyncram0:inst28
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
altsyncram
# storage
db|ads7844.(16).cnf
db|ads7844.(16).cnf
# case_insensitive
# source_file
c:|altera|71|quartus|libraries|megafunctions|altsyncram.tdf
b69478c2691550fb7f5ef3923da937a
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
3
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
8
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
16
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
3
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
8
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_s7m1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
c:|altera|71|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
c:|altera|71|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
c:|altera|71|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
c:|altera|71|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|71|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
c:|altera|71|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
c:|altera|71|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
c:|altera|71|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
c:|altera|71|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
d_latch:inst6|altsyncram0:inst33|altsyncram:altsyncram_component
d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component
d_latch:inst6|altsyncram0:inst31|altsyncram:altsyncram_component
d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component
d_latch:inst6|altsyncram0:inst29|altsyncram:altsyncram_component
d_latch:inst6|altsyncram0:inst30|altsyncram:altsyncram_component
d_latch:inst6|altsyncram0:inst26|altsyncram:altsyncram_component
d_latch:inst6|altsyncram0:inst28|altsyncram:altsyncram_component
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altsyncram_s7m1
# storage
db|ads7844.(17).cnf
db|ads7844.(17).cnf
# case_insensitive
# source_file
db|altsyncram_s7m1.tdf
8f8b9eb743eebbd9ab16f8e2d3f1ecf
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
d_latch:inst6|altsyncram0:inst33|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
d_latch:inst6|altsyncram0:inst31|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
d_latch:inst6|altsyncram0:inst29|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
d_latch:inst6|altsyncram0:inst30|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
d_latch:inst6|altsyncram0:inst26|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
d_latch:inst6|altsyncram0:inst28|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# complete