📄 ads7844.sim.vwf

📁 本源码介绍了ADS7844 AD转换芯片的VHDL控制器。
💻 VWF
📖 第 1 页 / 共 3 页
字号:
		LEVEL 1 FOR 1200.0;
		LEVEL 0 FOR 66000.0;
		LEVEL 1 FOR 800.0;
		LEVEL 0 FOR 31200.0;
	}
}

TRANSITION_LIST("dooo")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 100000.0;
	}
}

TRANSITION_LIST("addr[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 808.75;
		LEVEL 1 FOR 10953.078;
		LEVEL 0 FOR 56246.922;
		LEVEL 1 FOR 10553.078;
		LEVEL 0 FOR 21438.172;
	}
}

TRANSITION_LIST("addr[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 50164.865;
		LEVEL 1 FOR 17846.911;
		LEVEL 0 FOR 31988.224;
	}
}

TRANSITION_LIST("addr[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 30962.264;
		LEVEL 1 FOR 9600.0;
		LEVEL 0 FOR 0.257;
		LEVEL 1 FOR 9600.0;
		LEVEL 0 FOR 47599.743;
		LEVEL 1 FOR 2237.736;
	}
}

TRANSITION_LIST("addr[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 21362.548;
		LEVEL 1 FOR 9600.0;
		LEVEL 0 FOR 9599.792;
		LEVEL 1 FOR 9600.0;
		LEVEL 0 FOR 9600.462;
		LEVEL 1 FOR 8246.659;
		LEVEL 0 FOR 20153.087;
		LEVEL 1 FOR 9600.0;
		LEVEL 0 FOR 2237.452;
	}
}

TRANSITION_LIST("control_word[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 809.138;
		LEVEL 0 FOR 10953.078;
		LEVEL 1 FOR 56246.922;
		LEVEL 0 FOR 10553.078;
		LEVEL 1 FOR 21437.784;
	}
}

TRANSITION_LIST("control_word[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 21362.632;
		LEVEL 1 FOR 9600.0;
		LEVEL 0 FOR 9599.792;
		LEVEL 1 FOR 9600.0;
		LEVEL 0 FOR 9600.462;
		LEVEL 1 FOR 8246.659;
		LEVEL 0 FOR 20153.087;
		LEVEL 1 FOR 9600.0;
		LEVEL 0 FOR 2237.368;
	}
}

TRANSITION_LIST("control_word[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 50162.63;
		LEVEL 1 FOR 17846.911;
		LEVEL 0 FOR 31990.459;
	}
}

TRANSITION_LIST("control_word[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 30962.608;
		LEVEL 1 FOR 9600.0;
		LEVEL 0 FOR 0.257;
		LEVEL 1 FOR 9600.0;
		LEVEL 0 FOR 47599.743;
		LEVEL 1 FOR 2237.392;
	}
}

TRANSITION_LIST("control_word[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("control_word[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 809.107;
		LEVEL 0 FOR 10953.078;
		LEVEL 1 FOR 56246.922;
		LEVEL 0 FOR 10553.078;
		LEVEL 1 FOR 21437.815;
	}
}

TRANSITION_LIST("control_word[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("control_word[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("cs")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 11359.507;
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 400.0;
			LEVEL 0 FOR 9200.0;
		}
		LEVEL 1 FOR 400.0;
		LEVEL 0 FOR 18400.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 400.0;
			LEVEL 0 FOR 9200.0;
		}
		LEVEL 1 FOR 400.0;
		LEVEL 0 FOR 2240.493;
	}
}

TRANSITION_LIST("cs_ad")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 11363.243;
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 1400.182;
			LEVEL 0 FOR 8199.818;
		}
		LEVEL 1 FOR 1400.182;
		LEVEL 0 FOR 17399.818;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 1400.182;
			LEVEL 0 FOR 8199.818;
		}
		LEVEL 1 FOR 1400.182;
		LEVEL 0 FOR 1236.575;
	}
}

TRANSITION_LIST("stld")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 12159.785;
		NODE
		{
			REPEAT = 5;
			LEVEL 0 FOR 400.0;
			LEVEL 1 FOR 9200.0;
		}
		LEVEL 0 FOR 400.0;
		LEVEL 1 FOR 18400.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 400.0;
			LEVEL 1 FOR 9200.0;
		}
		LEVEL 0 FOR 400.0;
		LEVEL 1 FOR 1440.215;
	}
}

TRANSITION_LIST("d7[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d7[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("di")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 12164.307;
		LEVEL 1 FOR 994.372;
		LEVEL 0 FOR 1600.0;
		LEVEL 1 FOR 400.0;
		LEVEL 0 FOR 6605.628;
		LEVEL 1 FOR 1394.372;
		LEVEL 0 FOR 1200.0;
		LEVEL 1 FOR 400.0;
		LEVEL 0 FOR 6605.628;
		LEVEL 1 FOR 994.372;
		LEVEL 0 FOR 800.0;
		LEVEL 1 FOR 400.0;
		LEVEL 0 FOR 400.0;
		LEVEL 1 FOR 400.0;
		LEVEL 0 FOR 6605.628;
		LEVEL 1 FOR 1394.372;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 400.0;
			LEVEL 1 FOR 400.0;
		}
		LEVEL 0 FOR 6605.628;
		LEVEL 1 FOR 994.372;
		LEVEL 0 FOR 400.0;
		LEVEL 1 FOR 400.0;
		LEVEL 0 FOR 800.0;
		LEVEL 1 FOR 400.0;
		LEVEL 0 FOR 6605.628;
		LEVEL 1 FOR 1794.372;
		LEVEL 0 FOR 800.0;
		LEVEL 1 FOR 400.0;
		LEVEL 0 FOR 15805.628;
		LEVEL 1 FOR 994.372;
		LEVEL 0 FOR 1600.0;
		LEVEL 1 FOR 400.0;
		LEVEL 0 FOR 6605.628;
		LEVEL 1 FOR 1394.372;
		LEVEL 0 FOR 1200.0;
		LEVEL 1 FOR 400.0;
		LEVEL 0 FOR 6605.628;
		LEVEL 1 FOR 994.372;
		LEVEL 0 FOR 800.0;
		LEVEL 1 FOR 41.321;
	}
}

TRANSITION_LIST("d0[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("d0[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("q[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

TRANSITION_LIST("q[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 100000.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clk";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clk1";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "cs_all";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "dooo";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "addr";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 0;
	CHILDREN = 5, 6, 7, 8;
}

DISPLAY_LINE
{
	CHANNEL = "addr[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "addr[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 4;
}

DISPLAY_LINE
{
	CHANNEL = "addr[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 4;
}
💿 文件大小 1355 K
👤 上传用户 janeljh1
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#7844 #VHDL #ADS #源码
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