prev_cmp_ads7844.map.qmsg

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 39 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_shiftreg d_latch:inst6\|lpm_shiftreg0:inst55\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborating entity \"lpm_shiftreg\" for hierarchy \"d_latch:inst6\|lpm_shiftreg0:inst55\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "lpm_shiftreg0.vhd" "lpm_shiftreg_component" { Text "D:/我的先进院D盘/myaltera/ads7844/lpm_shiftreg0.vhd" 75 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "d_latch:inst6\|lpm_shiftreg0:inst55\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborated megafunction instantiation \"d_latch:inst6\|lpm_shiftreg0:inst55\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "lpm_shiftreg0.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/lpm_shiftreg0.vhd" 75 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_shiftreg2.vhd 2 1 " "Warning: Using design file lpm_shiftreg2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_shiftreg2-SYN " "Info: Found design unit 1: lpm_shiftreg2-SYN" {  } { { "lpm_shiftreg2.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/lpm_shiftreg2.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg2 " "Info: Found entity 1: lpm_shiftreg2" {  } { { "lpm_shiftreg2.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/lpm_shiftreg2.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_shiftreg2 d_latch:inst6\|lpm_shiftreg2:inst1 " "Info: Elaborating entity \"lpm_shiftreg2\" for hierarchy \"d_latch:inst6\|lpm_shiftreg2:inst1\"" {  } { { "d_latch.bdf" "inst1" { Schematic "D:/我的先进院D盘/myaltera/ads7844/d_latch.bdf" { { -336 248 392 -240 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/71/quartus/libraries/others/maxplus2/74465.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/others/maxplus2/74465.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74465 " "Info: Found entity 1: 74465" {  } { { "74465.bdf" "" { Schematic "c:/altera/71/quartus/libraries/others/maxplus2/74465.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74465 d_latch:inst6\|74465:inst14 " "Info: Elaborating entity \"74465\" for hierarchy \"d_latch:inst6\|74465:inst14\"" {  } { { "d_latch.bdf" "inst14" { Schematic "D:/我的先进院D盘/myaltera/ads7844/d_latch.bdf" { { -368 1040 1144 -176 "inst14" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "d_latch:inst6\|74465:inst14 " "Info: Elaborated megafunction instantiation \"d_latch:inst6\|74465:inst14\"" {  } { { "d_latch.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/d_latch.bdf" { { -368 1040 1144 -176 "inst14" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/71/quartus/libraries/others/maxplus2/74138.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/others/maxplus2/74138.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74138 " "Info: Found entity 1: 74138" {  } { { "74138.bdf" "" { Schematic "c:/altera/71/quartus/libraries/others/maxplus2/74138.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74138 d_latch:inst6\|74138:inst70 " "Info: Elaborating entity \"74138\" for hierarchy \"d_latch:inst6\|74138:inst70\"" {  } { { "d_latch.bdf" "inst70" { Schematic "D:/我的先进院D盘/myaltera/ads7844/d_latch.bdf" { { 256 -216 -96 416 "inst70" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "d_latch:inst6\|74138:inst70 " "Info: Elaborated megafunction instantiation \"d_latch:inst6\|74138:inst70\"" {  } { { "d_latch.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/d_latch.bdf" { { 256 -216 -96 416 "inst70" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "altsyncram0.vhd 2 1 " "Warning: Using design file altsyncram0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altsyncram0-SYN " "Info: Found design unit 1: altsyncram0-SYN" {  } { { "altsyncram0.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/altsyncram0.vhd" 54 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 altsyncram0 " "Info: Found entity 1: altsyncram0" {  } { { "altsyncram0.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/altsyncram0.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram0 d_latch:inst6\|altsyncram0:inst33 " "Info: Elaborating entity \"altsyncram0\" for hierarchy \"d_latch:inst6\|altsyncram0:inst33\"" {  } { { "d_latch.bdf" "inst33" { Schematic "D:/我的先进院D盘/myaltera/ads7844/d_latch.bdf" { { -360 592 848 -184 "inst33" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram d_latch:inst6\|altsyncram0:inst33\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"d_latch:inst6\|altsyncram0:inst33\|altsyncram:altsyncram_component\"" {  } { { "altsyncram0.vhd" "altsyncram_component" { Text "D:/我的先进院D盘/myaltera/ads7844/altsyncram0.vhd" 98 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "d_latch:inst6\|altsyncram0:inst33\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"d_latch:inst6\|altsyncram0:inst33\|altsyncram:altsyncram_component\"" {  } { { "altsyncram0.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/altsyncram0.vhd" 98 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_s7m1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_s7m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_s7m1 " "Info: Found entity 1: altsyncram_s7m1" {  } { { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_s7m1 d_latch:inst6\|altsyncram0:inst33\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated " "Info: Elaborating entity \"altsyncram_s7m1\" for hierarchy \"d_latch:inst6\|altsyncram0:inst33\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[15\] clear GND " "Warning: Reduced register \"d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[15\]\" with stuck clear port to stuck value GND" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 56 7 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[14\] clear GND " "Warning: Reduced register \"d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[14\]\" with stuck clear port to stuck value GND" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 56 7 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[13\] clear GND " "Warning: Reduced register \"d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[13\]\" with stuck clear port to stuck value GND" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 56 7 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[12\] clear GND " "Warning: Reduced register \"d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[12\]\" with stuck clear port to stuck value GND" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 56 7 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[11\] clear GND " "Warning: Reduced register \"d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[11\]\" with stuck clear port to stuck value GND" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 56 7 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[10\] clear GND " "Warning: Reduced register \"d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[10\]\" with stuck clear port to stuck value GND" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 56 7 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[9\] clear GND " "Warning: Reduced register \"d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[9\]\" with stuck clear port to stuck value GND" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 56 7 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[8\] clear GND " "Warning: Reduced register \"d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[8\]\" with stuck clear port to stuck value GND" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 56 7 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[7\] clear GND " "Warning: Reduced register \"d_latch:inst6\|lpm_shiftreg0:inst51\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[7\]\" with stuck clear port to stuck value GND" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 56 7 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}