ads7844.fit.qmsg

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fq_cs:inst3\|cs~reg0 Global clock " "Info: Automatically promoted some destinations of signal \"fq_cs:inst3\|cs~reg0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cs " "Info: Destination \"cs\" may be non-global or may not use global clock" {  } { { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 536 200 376 552 "cs" "" } { -56 288 336 -40 "cs" "" } { 192 296 344 208 "cs" "" } { -256 872 928 -240 "cs" "" } { 216 704 768 232 "cs" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fq_cs:inst3\|dff_2:u1\|q " "Info: Destination \"fq_cs:inst3\|dff_2:u1\|q\" may be non-global or may not use global clock" {  } { { "dff_2.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/dff_2.vhd" 6 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "d_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15 " "Info: Destination \"d_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15\" may be non-global or may not use global clock" {  } { { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 528 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "d_latch:inst6\|altsyncram0:inst30\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15 " "Info: Destination \"d_latch:inst6\|altsyncram0:inst30\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15\" may be non-global or may not use global clock" {  } { { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 528 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "d_latch:inst6\|altsyncram0:inst31\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15 " "Info: Destination \"d_latch:inst6\|altsyncram0:inst31\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15\" may be non-global or may not use global clock" {  } { { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 528 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "d_latch:inst6\|altsyncram0:inst28\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15 " "Info: Destination \"d_latch:inst6\|altsyncram0:inst28\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15\" may be non-global or may not use global clock" {  } { { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 528 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "d_latch:inst6\|altsyncram0:inst32\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15 " "Info: Destination \"d_latch:inst6\|altsyncram0:inst32\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15\" may be non-global or may not use global clock" {  } { { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 528 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "d_latch:inst6\|altsyncram0:inst26\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15 " "Info: Destination \"d_latch:inst6\|altsyncram0:inst26\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15\" may be non-global or may not use global clock" {  } { { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 528 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "d_latch:inst6\|altsyncram0:inst33\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15 " "Info: Destination \"d_latch:inst6\|altsyncram0:inst33\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15\" may be non-global or may not use global clock" {  } { { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 528 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "d_latch:inst6\|altsyncram0:inst29\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15 " "Info: Destination \"d_latch:inst6\|altsyncram0:inst29\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15\" may be non-global or may not use global clock" {  } { { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 528 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0 "" 0}  } { { "fq_cs.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/fq_cs.vhd" 66 0 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "cs_all Global clock " "Info: Automatically promoted signal \"cs_all\" to use Global clock" {  } { { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 472 200 368 488 "cs_all" "" } { 8 288 336 24 "cs_all" "" } { -248 696 744 -232 "cs_all" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "cs_all " "Info: Pin \"cs_all\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 472 200 368 488 "cs_all" "" } { 8 288 336 24 "cs_all" "" } { -248 696 744 -232 "cs_all" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "cs_all" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { cs_all } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { cs_all } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "cs_pulse:inst5\|inst3 Global clock " "Info: Automatically promoted signal \"cs_pulse:inst5\|inst3\" to use Global clock" {  } { { "cs_pulse.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/cs_pulse.bdf" { { 272 848 912 352 "inst3" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "to_ad:inst4\|74165b:inst\|102 Global clock " "Info: Automatically promoted signal \"to_ad:inst4\|74165b:inst\|102\" to use Global clock" {  } { { "74165b.bdf" "" { Schematic "c:/altera/71/quartus/libraries/others/maxplus2/74165b.bdf" { { 1368 376 440 1408 "102" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "to_ad:inst4\|74165b:inst\|103 Global clock " "Info: Automatically promoted signal \"to_ad:inst4\|74165b:inst\|103\" to use Global clock" {  } { { "74165b.bdf" "" { Schematic "c:/altera/71/quartus/libraries/others/maxplus2/74165b.bdf" { { 1256 296 360 1296 "103" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}