ads7844.fit.qmsg

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 28 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 28" {  } { { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 448 200 368 464 "clk" "" } { -192 376 432 -176 "clk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fq:inst\|clk_temp Global clock " "Info: Automatically promoted some destinations of signal \"fq:inst\|clk_temp\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clk1 " "Info: Destination \"clk1\" may be non-global or may not use global clock" {  } { { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 480 456 632 496 "clk1" "" } { -48 640 680 -32 "clk1" "" } { 224 296 344 240 "clk1" "" } { -200 696 744 -184 "clk1" "" } { -192 552 584 -176 "clk1" "" } { 184 704 768 200 "clk1" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fq:inst\|clk_temp " "Info: Destination \"fq:inst\|clk_temp\" may be non-global or may not use global clock" {  } { { "fq.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/fq.vhd" 52 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "fq.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/fq.vhd" 52 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rdclk Global clock " "Info: Automatically promoted signal \"rdclk\" to use Global clock" {  } { { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 480 712 880 496 "rdclk" "" } { 256 704 768 272 "rdclk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rdclk " "Info: Pin \"rdclk\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 480 712 880 496 "rdclk" "" } { 256 704 768 272 "rdclk" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "rdclk" } } } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclk } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclk } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "" 0}