ads7844.tan.qmsg

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

{ "Info" "ITDB_FULL_TCO_RESULT" "rdclk q\[5\] d_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a6~portb_address_reg0 16.898 ns memory " "Info: tco from clock \"rdclk\" to destination pin \"q\[5\]\" through memory \"d_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a6~portb_address_reg0\" is 16.898 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclk source 5.653 ns + Longest memory " "Info: + Longest clock path from clock \"rdclk\" to source memory is 5.653 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns rdclk 1 CLK PIN_125 12 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_125; Fanout = 12; CLK Node = 'rdclk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclk } "NODE_NAME" } } { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 480 712 880 496 "rdclk" "" } { 256 704 768 272 "rdclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.970 ns) + CELL(0.553 ns) 5.653 ns d_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a6~portb_address_reg0 2 MEM M4K_X17_Y11 36 " "Info: 2: + IC(3.970 ns) + CELL(0.553 ns) = 5.653 ns; Loc. = M4K_X17_Y11; Fanout = 36; MEM Node = 'd_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a6~portb_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.523 ns" { rdclk d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a6~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 240 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.683 ns ( 29.77 % ) " "Info: Total cell delay = 1.683 ns ( 29.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.970 ns ( 70.23 % ) " "Info: Total interconnect delay = 3.970 ns ( 70.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.653 ns" { rdclk d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a6~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.653 ns" { rdclk rdclk~out0 d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a6~portb_address_reg0 } { 0.000ns 0.000ns 3.970ns } { 0.000ns 1.130ns 0.553ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 240 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.745 ns + Longest memory pin " "Info: + Longest memory to pin delay is 10.745 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns d_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a6~portb_address_reg0 1 MEM M4K_X17_Y11 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y11; Fanout = 36; MEM Node = 'd_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a6~portb_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a6~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 240 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.321 ns) 3.321 ns d_latch:inst6\|altsyncram0:inst32\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|q_b\[5\] 2 MEM M4K_X17_Y11 1 " "Info: 2: + IC(0.000 ns) + CELL(3.321 ns) = 3.321 ns; Loc. = M4K_X17_Y11; Fanout = 1; MEM Node = 'd_latch:inst6\|altsyncram0:inst32\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|q_b\[5\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.321 ns" { d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a6~portb_address_reg0 d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[5] } "NODE_NAME" } } { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.603 ns) + CELL(0.454 ns) 5.378 ns d_latch:inst6\|74465:inst68\|19~118 3 COMB LC_X21_Y12_N6 1 " "Info: 3: + IC(1.603 ns) + CELL(0.454 ns) = 5.378 ns; Loc. = LC_X21_Y12_N6; Fanout = 1; COMB Node = 'd_latch:inst6\|74465:inst68\|19~118'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.057 ns" { d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[5] d_latch:inst6|74465:inst68|19~118 } "NODE_NAME" } } { "74465.bdf" "" { Schematic "c:/altera/71/quartus/libraries/others/maxplus2/74465.bdf" { { 328 264 312 360 "19" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.926 ns) + CELL(0.340 ns) 6.644 ns d_latch:inst6\|74465:inst68\|19~120 4 COMB LC_X21_Y11_N2 1 " "Info: 4: + IC(0.926 ns) + CELL(0.340 ns) = 6.644 ns; Loc. = LC_X21_Y11_N2; Fanout = 1; COMB Node = 'd_latch:inst6\|74465:inst68\|19~120'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { d_latch:inst6|74465:inst68|19~118 d_latch:inst6|74465:inst68|19~120 } "NODE_NAME" } } { "74465.bdf" "" { Schematic "c:/altera/71/quartus/libraries/others/maxplus2/74465.bdf" { { 328 264 312 360 "19" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.467 ns) + CELL(1.634 ns) 10.745 ns q\[5\] 5 PIN PIN_165 0 " "Info: 5: + IC(2.467 ns) + CELL(1.634 ns) = 10.745 ns; Loc. = PIN_165; Fanout = 0; PIN Node = 'q\[5\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.101 ns" { d_latch:inst6|74465:inst68|19~120 q[5] } "NODE_NAME" } } { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 536 712 888 552 "q\[15..0\]" "" } { 280 920 976 296 "q\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.749 ns ( 53.50 % ) " "Info: Total cell delay = 5.749 ns ( 53.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.996 ns ( 46.50 % ) " "Info: Total interconnect delay = 4.996 ns ( 46.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.745 ns" { d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a6~portb_address_reg0 d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[5] d_latch:inst6|74465:inst68|19~118 d_latch:inst6|74465:inst68|19~120 q[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.745 ns" { d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a6~portb_address_reg0 d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[5] d_latch:inst6|74465:inst68|19~118 d_latch:inst6|74465:inst68|19~120 q[5] } { 0.000ns 0.000ns 1.603ns 0.926ns 2.467ns } { 0.000ns 3.321ns 0.454ns 0.340ns 1.634ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.653 ns" { rdclk d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a6~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.653 ns" { rdclk rdclk~out0 d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a6~portb_address_reg0 } { 0.000ns 0.000ns 3.970ns } { 0.000ns 1.130ns 0.553ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.745 ns" { d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a6~portb_address_reg0 d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[5] d_latch:inst6|74465:inst68|19~118 d_latch:inst6|74465:inst68|19~120 q[5] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.745 ns" { d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a6~portb_address_reg0 d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|q_b[5] d_latch:inst6|74465:inst68|19~118 d_latch:inst6|74465:inst68|19~120 q[5] } { 0.000ns 0.000ns 1.603ns 0.926ns 2.467ns } { 0.000ns 3.321ns 0.454ns 0.340ns 1.634ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "addr_r\[0\] q\[10\] 15.189 ns Longest " "Info: Longest tpd from source pin \"addr_r\[0\]\" to destination pin \"q\[10\]\" is 15.189 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns addr_r\[0\] 1 PIN PIN_137 10 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_137; Fanout = 10; PIN Node = 'addr_r\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr_r[0] } "NODE_NAME" } } { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 456 712 880 472 "addr_r\[3..0\]" "" } { 184 920 986 200 "addr_r\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.542 ns) + CELL(0.454 ns) 7.126 ns d_latch:inst6\|74138:inst70\|21~129 2 COMB LC_X21_Y11_N8 16 " "Info: 2: + IC(5.542 ns) + CELL(0.454 ns) = 7.126 ns; Loc. = LC_X21_Y11_N8; Fanout = 16; COMB Node = 'd_latch:inst6\|74138:inst70\|21~129'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.996 ns" { addr_r[0] d_latch:inst6|74138:inst70|21~129 } "NODE_NAME" } } { "74138.bdf" "" { Schematic "c:/altera/71/quartus/libraries/others/maxplus2/74138.bdf" { { 448 568 632 520 "21" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.332 ns) + CELL(0.454 ns) 9.912 ns d_latch:inst6\|74465:inst69\|12~116 3 COMB LC_X19_Y9_N5 1 " "Info: 3: + IC(2.332 ns) + CELL(0.454 ns) = 9.912 ns; Loc. = LC_X19_Y9_N5; Fanout = 1; COMB Node = 'd_latch:inst6\|74465:inst69\|12~116'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.786 ns" { d_latch:inst6|74138:inst70|21~129 d_latch:inst6|74465:inst69|12~116 } "NODE_NAME" } } { "74465.bdf" "" { Schematic "c:/altera/71/quartus/libraries/others/maxplus2/74465.bdf" { { 184 264 312 216 "12" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.340 ns) 11.443 ns d_latch:inst6\|74465:inst69\|12~120 4 COMB LC_X21_Y10_N4 1 " "Info: 4: + IC(1.191 ns) + CELL(0.340 ns) = 11.443 ns; Loc. = LC_X21_Y10_N4; Fanout = 1; COMB Node = 'd_latch:inst6\|74465:inst69\|12~120'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.531 ns" { d_latch:inst6|74465:inst69|12~116 d_latch:inst6|74465:inst69|12~120 } "NODE_NAME" } } { "74465.bdf" "" { Schematic "c:/altera/71/quartus/libraries/others/maxplus2/74465.bdf" { { 184 264 312 216 "12" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.112 ns) + CELL(1.634 ns) 15.189 ns q\[10\] 5 PIN PIN_160 0 " "Info: 5: + IC(2.112 ns) + CELL(1.634 ns) = 15.189 ns; Loc. = PIN_160; Fanout = 0; PIN Node = 'q\[10\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.746 ns" { d_latch:inst6|74465:inst69|12~120 q[10] } "NODE_NAME" } } { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 536 712 888 552 "q\[15..0\]" "" } { 280 920 976 296 "q\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.012 ns ( 26.41 % ) " "Info: Total cell delay = 4.012 ns ( 26.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.177 ns ( 73.59 % ) " "Info: Total interconnect delay = 11.177 ns ( 73.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "15.189 ns" { addr_r[0] d_latch:inst6|74138:inst70|21~129 d_latch:inst6|74465:inst69|12~116 d_latch:inst6|74465:inst69|12~120 q[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "15.189 ns" { addr_r[0] addr_r[0]~out0 d_latch:inst6|74138:inst70|21~129 d_latch:inst6|74465:inst69|12~116 d_latch:inst6|74465:inst69|12~120 q[10] } { 0.000ns 0.000ns 5.542ns 2.332ns 1.191ns 2.112ns } { 0.000ns 1.130ns 0.454ns 0.454ns 0.340ns 1.634ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "d_latch:inst6\|altsyncram0:inst32\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a11~portb_address_reg0 addr_r\[0\] rdclk -0.994 ns memory " "Info: th for memory \"d_latch:inst6\|altsyncram0:inst32\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a11~portb_address_reg0\" (data pin = \"addr_r\[0\]\", clock pin = \"rdclk\") is -0.994 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclk destination 5.631 ns + Longest memory " "Info: + Longest clock path from clock \"rdclk\" to destination memory is 5.631 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns rdclk 1 CLK PIN_125 12 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_125; Fanout = 12; CLK Node = 'rdclk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclk } "NODE_NAME" } } { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 480 712 880 496 "rdclk" "" } { 256 704 768 272 "rdclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.948 ns) + CELL(0.553 ns) 5.631 ns d_latch:inst6\|altsyncram0:inst32\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a11~portb_address_reg0 2 MEM M4K_X17_Y9 36 " "Info: 2: + IC(3.948 ns) + CELL(0.553 ns) = 5.631 ns; Loc. = M4K_X17_Y9; Fanout = 36; MEM Node = 'd_latch:inst6\|altsyncram0:inst32\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a11~portb_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.501 ns" { rdclk d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a11~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 400 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.683 ns ( 29.89 % ) " "Info: Total cell delay = 1.683 ns ( 29.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.948 ns ( 70.11 % ) " "Info: Total interconnect delay = 3.948 ns ( 70.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.631 ns" { rdclk d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a11~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.631 ns" { rdclk rdclk~out0 d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a11~portb_address_reg0 } { 0.000ns 0.000ns 3.948ns } { 0.000ns 1.130ns 0.553ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.043 ns + " "Info: + Micro hold delay of destination is 0.043 ns" {  } { { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 400 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.668 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 6.668 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns addr_r\[0\] 1 PIN PIN_137 10 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_137; Fanout = 10; PIN Node = 'addr_r\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr_r[0] } "NODE_NAME" } } { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 456 712 880 472 "addr_r\[3..0\]" "" } { 184 920 986 200 "addr_r\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.284 ns) + CELL(0.254 ns) 6.668 ns d_latch:inst6\|altsyncram0:inst32\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a11~portb_address_reg0 2 MEM M4K_X17_Y9 36 " "Info: 2: + IC(5.284 ns) + CELL(0.254 ns) = 6.668 ns; Loc. = M4K_X17_Y9; Fanout = 36; MEM Node = 'd_latch:inst6\|altsyncram0:inst32\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a11~portb_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.538 ns" { addr_r[0] d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a11~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 400 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.384 ns ( 20.76 % ) " "Info: Total cell delay = 1.384 ns ( 20.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.284 ns ( 79.24 % ) " "Info: Total interconnect delay = 5.284 ns ( 79.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.668 ns" { addr_r[0] d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a11~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.668 ns" { addr_r[0] addr_r[0]~out0 d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a11~portb_address_reg0 } { 0.000ns 0.000ns 5.284ns } { 0.000ns 1.130ns 0.254ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.631 ns" { rdclk d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a11~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.631 ns" { rdclk rdclk~out0 d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a11~portb_address_reg0 } { 0.000ns 0.000ns 3.948ns } { 0.000ns 1.130ns 0.553ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.668 ns" { addr_r[0] d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a11~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.668 ns" { addr_r[0] addr_r[0]~out0 d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a11~portb_address_reg0 } { 0.000ns 0.000ns 5.284ns } { 0.000ns 1.130ns 0.254ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "108 " "Info: Allocated 108 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 14 16:19:37 2008 " "Info: Processing ended: Mon Jan 14 16:19:37 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}