ads7844.tan.qmsg

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fq_cs:inst3\|cs~reg0 " "Info: Detected ripple clock \"fq_cs:inst3\|cs~reg0\" as buffer" {  } { { "fq_cs.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/fq_cs.vhd" 66 0 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "fq_cs:inst3\|cs~reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "fq:inst\|clk_temp " "Info: Detected ripple clock \"fq:inst\|clk_temp\" as buffer" {  } { { "fq.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/fq.vhd" 52 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "fq:inst\|clk_temp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cs_pulse:inst5\|inst6 register to_ad:inst4\|74165b:inst\|96 95.27 MHz 10.496 ns Internal " "Info: Clock \"clk\" has Internal fmax of 95.27 MHz between source register \"cs_pulse:inst5\|inst6\" and destination register \"to_ad:inst4\|74165b:inst\|96\" (period= 10.496 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.612 ns + Longest register register " "Info: + Longest register to register delay is 1.612 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cs_pulse:inst5\|inst6 1 REG LC_X22_Y9_N4 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y9_N4; Fanout = 10; REG Node = 'cs_pulse:inst5\|inst6'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { cs_pulse:inst5|inst6 } "NODE_NAME" } } { "cs_pulse.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/cs_pulse.bdf" { { 272 528 592 352 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.945 ns) + CELL(0.667 ns) 1.612 ns to_ad:inst4\|74165b:inst\|96 2 REG LC_X20_Y9_N8 1 " "Info: 2: + IC(0.945 ns) + CELL(0.667 ns) = 1.612 ns; Loc. = LC_X20_Y9_N8; Fanout = 1; REG Node = 'to_ad:inst4\|74165b:inst\|96'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.612 ns" { cs_pulse:inst5|inst6 to_ad:inst4|74165b:inst|96 } "NODE_NAME" } } { "74165b.bdf" "" { Schematic "c:/altera/71/quartus/libraries/others/maxplus2/74165b.bdf" { { 952 712 776 1032 "96" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.667 ns ( 41.38 % ) " "Info: Total cell delay = 0.667 ns ( 41.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.945 ns ( 58.62 % ) " "Info: Total interconnect delay = 0.945 ns ( 58.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.612 ns" { cs_pulse:inst5|inst6 to_ad:inst4|74165b:inst|96 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.612 ns" { cs_pulse:inst5|inst6 to_ad:inst4|74165b:inst|96 } { 0.000ns 0.945ns } { 0.000ns 0.667ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.434 ns - Smallest " "Info: - Smallest clock skew is -3.434 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.664 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.664 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_28 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_28; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 448 200 368 464 "clk" "" } { -192 376 432 -176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.720 ns) 2.421 ns fq:inst\|clk_temp 2 REG LC_X8_Y10_N7 288 " "Info: 2: + IC(0.571 ns) + CELL(0.720 ns) = 2.421 ns; Loc. = LC_X8_Y10_N7; Fanout = 288; REG Node = 'fq:inst\|clk_temp'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.291 ns" { clk fq:inst|clk_temp } "NODE_NAME" } } { "fq.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/fq.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.696 ns) + CELL(0.547 ns) 5.664 ns to_ad:inst4\|74165b:inst\|96 3 REG LC_X20_Y9_N8 1 " "Info: 3: + IC(2.696 ns) + CELL(0.547 ns) = 5.664 ns; Loc. = LC_X20_Y9_N8; Fanout = 1; REG Node = 'to_ad:inst4\|74165b:inst\|96'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.243 ns" { fq:inst|clk_temp to_ad:inst4|74165b:inst|96 } "NODE_NAME" } } { "74165b.bdf" "" { Schematic "c:/altera/71/quartus/libraries/others/maxplus2/74165b.bdf" { { 952 712 776 1032 "96" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.397 ns ( 42.32 % ) " "Info: Total cell delay = 2.397 ns ( 42.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.267 ns ( 57.68 % ) " "Info: Total interconnect delay = 3.267 ns ( 57.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.664 ns" { clk fq:inst|clk_temp to_ad:inst4|74165b:inst|96 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.664 ns" { clk clk~out0 fq:inst|clk_temp to_ad:inst4|74165b:inst|96 } { 0.000ns 0.000ns 0.571ns 2.696ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.098 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 9.098 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_28 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_28; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 448 200 368 464 "clk" "" } { -192 376 432 -176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.720 ns) 2.421 ns fq:inst\|clk_temp 2 REG LC_X8_Y10_N7 288 " "Info: 2: + IC(0.571 ns) + CELL(0.720 ns) = 2.421 ns; Loc. = LC_X8_Y10_N7; Fanout = 288; REG Node = 'fq:inst\|clk_temp'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.291 ns" { clk fq:inst|clk_temp } "NODE_NAME" } } { "fq.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/fq.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.705 ns) + CELL(0.720 ns) 5.846 ns fq_cs:inst3\|cs~reg0 3 REG LC_X8_Y10_N2 152 " "Info: 3: + IC(2.705 ns) + CELL(0.720 ns) = 5.846 ns; Loc. = LC_X8_Y10_N2; Fanout = 152; REG Node = 'fq_cs:inst3\|cs~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.425 ns" { fq:inst|clk_temp fq_cs:inst3|cs~reg0 } "NODE_NAME" } } { "fq_cs.vhd" "" { Text "D:/我的先进院D盘/myaltera/ads7844/fq_cs.vhd" 66 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.705 ns) + CELL(0.547 ns) 9.098 ns cs_pulse:inst5\|inst6 4 REG LC_X22_Y9_N4 10 " "Info: 4: + IC(2.705 ns) + CELL(0.547 ns) = 9.098 ns; Loc. = LC_X22_Y9_N4; Fanout = 10; REG Node = 'cs_pulse:inst5\|inst6'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.252 ns" { fq_cs:inst3|cs~reg0 cs_pulse:inst5|inst6 } "NODE_NAME" } } { "cs_pulse.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/cs_pulse.bdf" { { 272 528 592 352 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.117 ns ( 34.26 % ) " "Info: Total cell delay = 3.117 ns ( 34.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.981 ns ( 65.74 % ) " "Info: Total interconnect delay = 5.981 ns ( 65.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.098 ns" { clk fq:inst|clk_temp fq_cs:inst3|cs~reg0 cs_pulse:inst5|inst6 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.098 ns" { clk clk~out0 fq:inst|clk_temp fq_cs:inst3|cs~reg0 cs_pulse:inst5|inst6 } { 0.000ns 0.000ns 0.571ns 2.705ns 2.705ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.664 ns" { clk fq:inst|clk_temp to_ad:inst4|74165b:inst|96 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.664 ns" { clk clk~out0 fq:inst|clk_temp to_ad:inst4|74165b:inst|96 } { 0.000ns 0.000ns 0.571ns 2.696ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.098 ns" { clk fq:inst|clk_temp fq_cs:inst3|cs~reg0 cs_pulse:inst5|inst6 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.098 ns" { clk clk~out0 fq:inst|clk_temp fq_cs:inst3|cs~reg0 cs_pulse:inst5|inst6 } { 0.000ns 0.000ns 0.571ns 2.705ns 2.705ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "cs_pulse.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/cs_pulse.bdf" { { 272 528 592 352 "inst6" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "74165b.bdf" "" { Schematic "c:/altera/71/quartus/libraries/others/maxplus2/74165b.bdf" { { 952 712 776 1032 "96" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "cs_pulse.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/cs_pulse.bdf" { { 272 528 592 352 "inst6" "" } } } } { "74165b.bdf" "" { Schematic "c:/altera/71/quartus/libraries/others/maxplus2/74165b.bdf" { { 952 712 776 1032 "96" "" } } } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.612 ns" { cs_pulse:inst5|inst6 to_ad:inst4|74165b:inst|96 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.612 ns" { cs_pulse:inst5|inst6 to_ad:inst4|74165b:inst|96 } { 0.000ns 0.945ns } { 0.000ns 0.667ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.664 ns" { clk fq:inst|clk_temp to_ad:inst4|74165b:inst|96 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.664 ns" { clk clk~out0 fq:inst|clk_temp to_ad:inst4|74165b:inst|96 } { 0.000ns 0.000ns 0.571ns 2.696ns } { 0.000ns 1.130ns 0.720ns 0.547ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.098 ns" { clk fq:inst|clk_temp fq_cs:inst3|cs~reg0 cs_pulse:inst5|inst6 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.098 ns" { clk clk~out0 fq:inst|clk_temp fq_cs:inst3|cs~reg0 cs_pulse:inst5|inst6 } { 0.000ns 0.000ns 0.571ns 2.705ns 2.705ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "rdclk " "Info: No valid register-to-register data paths exist for clock \"rdclk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "d_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15~portb_address_reg0 rden rdclk 2.472 ns memory " "Info: tsu for memory \"d_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15~portb_address_reg0\" (data pin = \"rden\", clock pin = \"rdclk\") is 2.472 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.053 ns + Longest pin memory " "Info: + Longest pin to memory delay is 8.053 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns rden 1 PIN PIN_126 12 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_126; Fanout = 12; PIN Node = 'rden'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rden } "NODE_NAME" } } { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 512 712 880 528 "rden" "" } { 280 704 768 296 "rden" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.183 ns) + CELL(0.740 ns) 8.053 ns d_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15~portb_address_reg0 2 MEM M4K_X17_Y10 36 " "Info: 2: + IC(6.183 ns) + CELL(0.740 ns) = 8.053 ns; Loc. = M4K_X17_Y10; Fanout = 36; MEM Node = 'd_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15~portb_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.923 ns" { rden d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a15~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 528 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.870 ns ( 23.22 % ) " "Info: Total cell delay = 1.870 ns ( 23.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.183 ns ( 76.78 % ) " "Info: Total interconnect delay = 6.183 ns ( 76.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.053 ns" { rden d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a15~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.053 ns" { rden rden~out0 d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a15~portb_address_reg0 } { 0.000ns 0.000ns 6.183ns } { 0.000ns 1.130ns 0.740ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.072 ns + " "Info: + Micro setup delay of destination is 0.072 ns" {  } { { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 528 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclk destination 5.653 ns - Shortest memory " "Info: - Shortest clock path from clock \"rdclk\" to destination memory is 5.653 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns rdclk 1 CLK PIN_125 12 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_125; Fanout = 12; CLK Node = 'rdclk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclk } "NODE_NAME" } } { "ads7844.bdf" "" { Schematic "D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf" { { 480 712 880 496 "rdclk" "" } { 256 704 768 272 "rdclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.970 ns) + CELL(0.553 ns) 5.653 ns d_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15~portb_address_reg0 2 MEM M4K_X17_Y10 36 " "Info: 2: + IC(3.970 ns) + CELL(0.553 ns) = 5.653 ns; Loc. = M4K_X17_Y10; Fanout = 36; MEM Node = 'd_latch:inst6\|altsyncram0:inst34\|altsyncram:altsyncram_component\|altsyncram_s7m1:auto_generated\|ram_block1a15~portb_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.523 ns" { rdclk d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a15~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_s7m1.tdf" "" { Text "D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf" 528 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.683 ns ( 29.77 % ) " "Info: Total cell delay = 1.683 ns ( 29.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.970 ns ( 70.23 % ) " "Info: Total interconnect delay = 3.970 ns ( 70.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.653 ns" { rdclk d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a15~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.653 ns" { rdclk rdclk~out0 d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a15~portb_address_reg0 } { 0.000ns 0.000ns 3.970ns } { 0.000ns 1.130ns 0.553ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.053 ns" { rden d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a15~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.053 ns" { rden rden~out0 d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a15~portb_address_reg0 } { 0.000ns 0.000ns 6.183ns } { 0.000ns 1.130ns 0.740ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.653 ns" { rdclk d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a15~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.653 ns" { rdclk rdclk~out0 d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a15~portb_address_reg0 } { 0.000ns 0.000ns 3.970ns } { 0.000ns 1.130ns 0.553ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}