ads7844.hier_info

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
clock1 => ram_block1a8.CLK1
clock1 => ram_block1a9.CLK1
clock1 => ram_block1a10.CLK1
clock1 => ram_block1a11.CLK1
clock1 => ram_block1a12.CLK1
clock1 => ram_block1a13.CLK1
clock1 => ram_block1a14.CLK1
clock1 => ram_block1a15.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
q_b[8] <= ram_block1a8.PORTBDATAOUT
q_b[9] <= ram_block1a9.PORTBDATAOUT
q_b[10] <= ram_block1a10.PORTBDATAOUT
q_b[11] <= ram_block1a11.PORTBDATAOUT
q_b[12] <= ram_block1a12.PORTBDATAOUT
q_b[13] <= ram_block1a13.PORTBDATAOUT
q_b[14] <= ram_block1a14.PORTBDATAOUT
q_b[15] <= ram_block1a15.PORTBDATAOUT
rden_b => ram_block1a0.ENA1
rden_b => ram_block1a1.ENA1
rden_b => ram_block1a2.ENA1
rden_b => ram_block1a3.ENA1
rden_b => ram_block1a4.ENA1
rden_b => ram_block1a5.ENA1
rden_b => ram_block1a6.ENA1
rden_b => ram_block1a7.ENA1
rden_b => ram_block1a8.ENA1
rden_b => ram_block1a9.ENA1
rden_b => ram_block1a10.ENA1
rden_b => ram_block1a11.ENA1
rden_b => ram_block1a12.ENA1
rden_b => ram_block1a13.ENA1
rden_b => ram_block1a14.ENA1
rden_b => ram_block1a15.ENA1
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.ENA0
wren_a => ram_block1a8.ENA0
wren_a => ram_block1a9.ENA0
wren_a => ram_block1a10.ENA0
wren_a => ram_block1a11.ENA0
wren_a => ram_block1a12.ENA0
wren_a => ram_block1a13.ENA0
wren_a => ram_block1a14.ENA0
wren_a => ram_block1a15.ENA0


|ads7844|d_latch:inst6|lpm_shiftreg0:inst22
aclr => lpm_shiftreg:lpm_shiftreg_component.aclr
clock => lpm_shiftreg:lpm_shiftreg_component.clock
enable => lpm_shiftreg:lpm_shiftreg_component.enable
shiftin => lpm_shiftreg:lpm_shiftreg_component.shiftin
q[0] <= lpm_shiftreg:lpm_shiftreg_component.q[0]
q[1] <= lpm_shiftreg:lpm_shiftreg_component.q[1]
q[2] <= lpm_shiftreg:lpm_shiftreg_component.q[2]
q[3] <= lpm_shiftreg:lpm_shiftreg_component.q[3]
q[4] <= lpm_shiftreg:lpm_shiftreg_component.q[4]
q[5] <= lpm_shiftreg:lpm_shiftreg_component.q[5]
q[6] <= lpm_shiftreg:lpm_shiftreg_component.q[6]
q[7] <= lpm_shiftreg:lpm_shiftreg_component.q[7]
q[8] <= lpm_shiftreg:lpm_shiftreg_component.q[8]
q[9] <= lpm_shiftreg:lpm_shiftreg_component.q[9]
q[10] <= lpm_shiftreg:lpm_shiftreg_component.q[10]
q[11] <= lpm_shiftreg:lpm_shiftreg_component.q[11]
q[12] <= lpm_shiftreg:lpm_shiftreg_component.q[12]
q[13] <= lpm_shiftreg:lpm_shiftreg_component.q[13]
q[14] <= lpm_shiftreg:lpm_shiftreg_component.q[14]
q[15] <= lpm_shiftreg:lpm_shiftreg_component.q[15]


|ads7844|d_latch:inst6|lpm_shiftreg0:inst22|lpm_shiftreg:lpm_shiftreg_component
clock => dffs[15].CLK
clock => dffs[14].CLK
clock => dffs[13].CLK
clock => dffs[12].CLK
clock => dffs[11].CLK
clock => dffs[10].CLK
clock => dffs[9].CLK
clock => dffs[8].CLK
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[15].ENA
enable => dffs[14].ENA
enable => dffs[13].ENA
enable => dffs[12].ENA
enable => dffs[11].ENA
enable => dffs[10].ENA
enable => dffs[9].ENA
enable => dffs[8].ENA
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
aset => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffs[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffs[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= dffs[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= dffs[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= dffs[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= dffs[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= dffs[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= dffs[15].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|ads7844|d_latch:inst6|74465:inst58
Y6 <= 19.DB_MAX_OUTPUT_PORT_TYPE
A6 => 19.DATAIN
GN1 => 2.IN0
GN2 => 2.IN1
Y5 <= 18.DB_MAX_OUTPUT_PORT_TYPE
A5 => 18.DATAIN
Y4 <= 13.DB_MAX_OUTPUT_PORT_TYPE
A4 => 13.DATAIN
Y3 <= 12.DB_MAX_OUTPUT_PORT_TYPE
A3 => 12.DATAIN
Y2 <= 7.DB_MAX_OUTPUT_PORT_TYPE
A2 => 7.DATAIN
Y1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
A1 => 4.DATAIN
Y7 <= 22.DB_MAX_OUTPUT_PORT_TYPE
A7 => 22.DATAIN
Y8 <= 23.DB_MAX_OUTPUT_PORT_TYPE
A8 => 23.DATAIN


|ads7844|d_latch:inst6|altsyncram0:inst31
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
data[8] => altsyncram:altsyncram_component.data_a[8]
data[9] => altsyncram:altsyncram_component.data_a[9]
data[10] => altsyncram:altsyncram_component.data_a[10]
data[11] => altsyncram:altsyncram_component.data_a[11]
data[12] => altsyncram:altsyncram_component.data_a[12]
data[13] => altsyncram:altsyncram_component.data_a[13]
data[14] => altsyncram:altsyncram_component.data_a[14]
data[15] => altsyncram:altsyncram_component.data_a[15]
rdaddress[0] => altsyncram:altsyncram_component.address_b[0]
rdaddress[1] => altsyncram:altsyncram_component.address_b[1]
rdaddress[2] => altsyncram:altsyncram_component.address_b[2]
rdclock => altsyncram:altsyncram_component.clock1
rden => altsyncram:altsyncram_component.rden_b
wraddress[0] => altsyncram:altsyncram_component.address_a[0]
wraddress[1] => altsyncram:altsyncram_component.address_a[1]
wraddress[2] => altsyncram:altsyncram_component.address_a[2]
wrclock => altsyncram:altsyncram_component.clock0
wren => altsyncram:altsyncram_component.wren_a
q[0] <= altsyncram:altsyncram_component.q_b[0]
q[1] <= altsyncram:altsyncram_component.q_b[1]
q[2] <= altsyncram:altsyncram_component.q_b[2]
q[3] <= altsyncram:altsyncram_component.q_b[3]
q[4] <= altsyncram:altsyncram_component.q_b[4]
q[5] <= altsyncram:altsyncram_component.q_b[5]
q[6] <= altsyncram:altsyncram_component.q_b[6]
q[7] <= altsyncram:altsyncram_component.q_b[7]
q[8] <= altsyncram:altsyncram_component.q_b[8]
q[9] <= altsyncram:altsyncram_component.q_b[9]
q[10] <= altsyncram:altsyncram_component.q_b[10]
q[11] <= altsyncram:altsyncram_component.q_b[11]
q[12] <= altsyncram:altsyncram_component.q_b[12]
q[13] <= altsyncram:altsyncram_component.q_b[13]
q[14] <= altsyncram:altsyncram_component.q_b[14]
q[15] <= altsyncram:altsyncram_component.q_b[15]


|ads7844|d_latch:inst6|altsyncram0:inst31|altsyncram:altsyncram_component
wren_a => altsyncram_s7m1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => altsyncram_s7m1:auto_generated.rden_b
data_a[0] => altsyncram_s7m1:auto_generated.data_a[0]
data_a[1] => altsyncram_s7m1:auto_generated.data_a[1]
data_a[2] => altsyncram_s7m1:auto_generated.data_a[2]
data_a[3] => altsyncram_s7m1:auto_generated.data_a[3]
data_a[4] => altsyncram_s7m1:auto_generated.data_a[4]
data_a[5] => altsyncram_s7m1:auto_generated.data_a[5]
data_a[6] => altsyncram_s7m1:auto_generated.data_a[6]
data_a[7] => altsyncram_s7m1:auto_generated.data_a[7]
data_a[8] => altsyncram_s7m1:auto_generated.data_a[8]
data_a[9] => altsyncram_s7m1:auto_generated.data_a[9]
data_a[10] => altsyncram_s7m1:auto_generated.data_a[10]
data_a[11] => altsyncram_s7m1:auto_generated.data_a[11]
data_a[12] => altsyncram_s7m1:auto_generated.data_a[12]
data_a[13] => altsyncram_s7m1:auto_generated.data_a[13]
data_a[14] => altsyncram_s7m1:auto_generated.data_a[14]
data_a[15] => altsyncram_s7m1:auto_generated.data_a[15]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
data_b[8] => ~NO_FANOUT~
data_b[9] => ~NO_FANOUT~
data_b[10] => ~NO_FANOUT~
data_b[11] => ~NO_FANOUT~
data_b[12] => ~NO_FANOUT~
data_b[13] => ~NO_FANOUT~
data_b[14] => ~NO_FANOUT~
data_b[15] => ~NO_FANOUT~
address_a[0] => altsyncram_s7m1:auto_generated.address_a[0]
address_a[1] => altsyncram_s7m1:auto_generated.address_a[1]
address_a[2] => altsyncram_s7m1:auto_generated.address_a[2]
address_b[0] => altsyncram_s7m1:auto_generated.address_b[0]
address_b[1] => altsyncram_s7m1:auto_generated.address_b[1]
address_b[2] => altsyncram_s7m1:auto_generated.address_b[2]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_s7m1:auto_generated.clock0
clock1 => altsyncram_s7m1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_a[8] <= <GND>
q_a[9] <= <GND>
q_a[10] <= <GND>
q_a[11] <= <GND>