ads7844.hier_info

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

|ads7844
cs <= fq_cs:inst3.cs
clk1 <= fq:inst.clk1
clk => fq:inst.clk
cs_all => fq_cs:inst3.cs_all
cs_all => addr_1:inst1.cs_all
di <= to_ad:inst4.di
stld <= fq_cs:inst3.stld
cs_ad <= cs_pulse:inst5.cs_ad
control_word[0] <= addr_1:inst1.control_word[0]
control_word[1] <= addr_1:inst1.control_word[1]
control_word[2] <= addr_1:inst1.control_word[2]
control_word[3] <= addr_1:inst1.control_word[3]
control_word[4] <= addr_1:inst1.control_word[4]
control_word[5] <= addr_1:inst1.control_word[5]
control_word[6] <= addr_1:inst1.control_word[6]
control_word[7] <= addr_1:inst1.control_word[7]
addr[0] <= addr_1:inst1.addr[0]
addr[1] <= addr_1:inst1.addr[1]
addr[2] <= addr_1:inst1.addr[2]
addr[3] <= addr_1:inst1.addr[3]
d0[0] <= d_latch:inst6.d0[0]
d0[1] <= d_latch:inst6.d0[1]
d0[2] <= d_latch:inst6.d0[2]
d0[3] <= d_latch:inst6.d0[3]
d0[4] <= d_latch:inst6.d0[4]
d0[5] <= d_latch:inst6.d0[5]
d0[6] <= d_latch:inst6.d0[6]
d0[7] <= d_latch:inst6.d0[7]
d0[8] <= d_latch:inst6.d0[8]
d0[9] <= d_latch:inst6.d0[9]
d0[10] <= d_latch:inst6.d0[10]
d0[11] <= d_latch:inst6.d0[11]
d0[12] <= d_latch:inst6.d0[12]
d0[13] <= d_latch:inst6.d0[13]
d0[14] <= d_latch:inst6.d0[14]
d0[15] <= d_latch:inst6.d0[15]
rden => d_latch:inst6.rden
rdclk => d_latch:inst6.rdclk
dooo => d_latch:inst6.dooo
ad_do[0] => d_latch:inst6.ad_do[0]
ad_do[1] => d_latch:inst6.ad_do[1]
ad_do[2] => d_latch:inst6.ad_do[2]
ad_do[3] => d_latch:inst6.ad_do[3]
ad_do[4] => d_latch:inst6.ad_do[4]
ad_do[5] => d_latch:inst6.ad_do[5]
ad_do[6] => d_latch:inst6.ad_do[6]
ad_do[7] => d_latch:inst6.ad_do[7]
addr_r[0] => d_latch:inst6.addr_r[0]
addr_r[1] => d_latch:inst6.addr_r[1]
addr_r[2] => d_latch:inst6.addr_r[2]
addr_r[3] => d_latch:inst6.addr_r[3]
d7[0] <= d_latch:inst6.d7[0]
d7[1] <= d_latch:inst6.d7[1]
d7[2] <= d_latch:inst6.d7[2]
d7[3] <= d_latch:inst6.d7[3]
d7[4] <= d_latch:inst6.d7[4]
d7[5] <= d_latch:inst6.d7[5]
d7[6] <= d_latch:inst6.d7[6]
d7[7] <= d_latch:inst6.d7[7]
d7[8] <= d_latch:inst6.d7[8]
d7[9] <= d_latch:inst6.d7[9]
d7[10] <= d_latch:inst6.d7[10]
d7[11] <= d_latch:inst6.d7[11]
d7[12] <= d_latch:inst6.d7[12]
d7[13] <= d_latch:inst6.d7[13]
d7[14] <= d_latch:inst6.d7[14]
d7[15] <= d_latch:inst6.d7[15]
q[0] <= d_latch:inst6.q[0]
q[1] <= d_latch:inst6.q[1]
q[2] <= d_latch:inst6.q[2]
q[3] <= d_latch:inst6.q[3]
q[4] <= d_latch:inst6.q[4]
q[5] <= d_latch:inst6.q[5]
q[6] <= d_latch:inst6.q[6]
q[7] <= d_latch:inst6.q[7]
q[8] <= d_latch:inst6.q[8]
q[9] <= d_latch:inst6.q[9]
q[10] <= d_latch:inst6.q[10]
q[11] <= d_latch:inst6.q[11]
q[12] <= d_latch:inst6.q[12]
q[13] <= d_latch:inst6.q[13]
q[14] <= d_latch:inst6.q[14]
q[15] <= d_latch:inst6.q[15]


|ads7844|fq_cs:inst3
clk2 => dff_2:u2.clk
clk2 => q[4].CLK
clk2 => q[3].CLK
clk2 => q[2].CLK
clk2 => q[1].CLK
clk2 => q[0].CLK
clk2 => cs~reg0.CLK
clk2 => dff_2:u1.clk
cs_all => q[4].ACLR
cs_all => q[3].ACLR
cs_all => q[2].ACLR
cs_all => q[1].ACLR
cs_all => q[0].ACLR
cs_all => cs~reg0.ACLR
cs <= comb~1
stld <= dff_2:u2.q


|ads7844|fq_cs:inst3|dff_2:u1
d => q~reg0.DATAIN
clk => q~reg0.CLK
q <= q~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ads7844|fq_cs:inst3|dff_2:u2
d => q~reg0.DATAIN
clk => q~reg0.CLK
q <= q~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ads7844|fq:inst
clk => counter[3].CLK
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => clk_temp.CLK
clk1 <= clk_temp.DB_MAX_OUTPUT_PORT_TYPE


|ads7844|to_ad:inst4
di <= 74165b:inst.Q7
clk1 => inst2.IN0
stld => 74165b:inst.STLD
cs_ad => 74165b:inst.CLKIH
control_word[0] => 74165b:inst.D[0]
control_word[1] => 74165b:inst.D[1]
control_word[2] => 74165b:inst.D[2]
control_word[3] => 74165b:inst.D[3]
control_word[4] => 74165b:inst.D[4]
control_word[5] => 74165b:inst.D[5]
control_word[6] => 74165b:inst.D[6]
control_word[7] => 74165b:inst.D[7]


|ads7844|to_ad:inst4|74165b:inst
Q7 <= 94.DB_MAX_OUTPUT_PORT_TYPE
D7 => 103.IN0
STLD => 56.IN0
CLK => 94.CLK
CLK => 95.CLK
CLK => 96.CLK
CLK => 97.CLK
CLK => 98.CLK
CLK => 99.CLK
CLK => 100.CLK
CLK => 101.CLK
D6 => 104.IN0
D5 => 107.IN0
D4 => 108.IN0
D3 => 111.IN0
D2 => 112.IN0
D1 => 115.IN0
D0 => 117.IN0
SER => 85.IN0
CLKIH => 55.IN0
CLKIH => 84.IN0
CLKIH => 83.IN0
CLKIH => 80.IN0
CLKIH => 79.IN0
CLKIH => 76.IN0
CLKIH => 75.IN0
CLKIH => 72.IN0
CLKIH => 71.IN0
Q7N <= 54.DB_MAX_OUTPUT_PORT_TYPE


|ads7844|cs_pulse:inst5
cs_ad <= inst6.DB_MAX_OUTPUT_PORT_TYPE
clk1 => inst1.IN0
clk1 => cs_wide:inst.clk
cs => inst6.CLK


|ads7844|cs_pulse:inst5|cs_wide:inst
ena => co~reg0.ENA
ena => q[1].ENA
ena => q[0].ENA
clrn => q[1].ACLR
clrn => q[0].ACLR
clrn => co~reg0.ACLR
clk => q[1].CLK
clk => q[0].CLK
clk => co~reg0.CLK
cai => ~NO_FANOUT~
co <= co~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ads7844|addr_1:inst1
cs => current_state~0.IN1
cs_all => current_state~1.IN1
addr[0] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
addr[1] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
addr[2] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
addr[3] <= current_state.s0.DB_MAX_OUTPUT_PORT_TYPE
control_word[0] <= <GND>
control_word[1] <= <GND>
control_word[2] <= current_state.s0.DB_MAX_OUTPUT_PORT_TYPE
control_word[3] <= <GND>
control_word[4] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
control_word[5] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
control_word[6] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
control_word[7] <= current_state.s0.DB_MAX_OUTPUT_PORT_TYPE


|ads7844|d_latch:inst6
d0[0] <= lpm_shiftreg0:inst55.q[0]
d0[1] <= lpm_shiftreg0:inst55.q[1]
d0[2] <= lpm_shiftreg0:inst55.q[2]
d0[3] <= lpm_shiftreg0:inst55.q[3]
d0[4] <= lpm_shiftreg0:inst55.q[4]
d0[5] <= lpm_shiftreg0:inst55.q[5]
d0[6] <= lpm_shiftreg0:inst55.q[6]
d0[7] <= lpm_shiftreg0:inst55.q[7]
d0[8] <= lpm_shiftreg0:inst55.q[8]
d0[9] <= lpm_shiftreg0:inst55.q[9]
d0[10] <= lpm_shiftreg0:inst55.q[10]
d0[11] <= lpm_shiftreg0:inst55.q[11]
d0[12] <= lpm_shiftreg0:inst55.q[12]
d0[13] <= lpm_shiftreg0:inst55.q[13]
d0[14] <= lpm_shiftreg0:inst55.q[14]
d0[15] <= lpm_shiftreg0:inst55.q[15]
clk1 => lpm_shiftreg0:inst55.clock
clk1 => lpm_shiftreg2:inst1.clock
clk1 => altsyncram0:inst33.wrclock
clk1 => altsyncram0:inst34.wrclock
clk1 => lpm_shiftreg0:inst22.clock
clk1 => altsyncram0:inst31.wrclock
clk1 => lpm_shiftreg0:inst35.clock
clk1 => altsyncram0:inst32.wrclock
clk1 => lpm_shiftreg0:inst39.clock
clk1 => altsyncram0:inst29.wrclock
clk1 => lpm_shiftreg0:inst43.clock
clk1 => altsyncram0:inst30.wrclock
clk1 => lpm_shiftreg0:inst47.clock
clk1 => altsyncram0:inst26.wrclock
clk1 => lpm_shiftreg0:inst51.clock
clk1 => altsyncram0:inst28.wrclock
cs_ad => inst54.IN0
cs_ad => inst2.IN0
cs_ad => inst21.IN0
cs_ad => inst25.IN0
cs_ad => inst38.IN0
cs_ad => inst42.IN0
cs_ad => inst46.IN0
cs_ad => inst50.IN0
ad_do[0] => lpm_shiftreg0:inst55.shiftin
ad_do[1] => lpm_shiftreg0:inst51.shiftin
ad_do[2] => lpm_shiftreg0:inst47.shiftin
ad_do[3] => lpm_shiftreg0:inst43.shiftin
ad_do[4] => lpm_shiftreg0:inst39.shiftin
ad_do[5] => lpm_shiftreg0:inst35.shiftin
ad_do[6] => lpm_shiftreg0:inst22.shiftin
ad_do[7] => ~NO_FANOUT~
cs_all => inst57.IN0
cs_all => inst4.IN0
cs_all => inst24.IN0
cs_all => inst37.IN0
cs_all => inst41.IN0
cs_all => inst45.IN0
cs_all => inst49.IN0
cs_all => inst53.IN0
stld => inst56.IN0
stld => inst3.IN0
stld => inst23.IN0
stld => inst36.IN0
stld => inst40.IN0
stld => inst44.IN0
stld => inst48.IN0
stld => inst52.IN0
d7[0] <= lpm_shiftreg2:inst1.q[0]
d7[1] <= lpm_shiftreg2:inst1.q[1]
d7[2] <= lpm_shiftreg2:inst1.q[2]
d7[3] <= lpm_shiftreg2:inst1.q[3]
d7[4] <= lpm_shiftreg2:inst1.q[4]
d7[5] <= lpm_shiftreg2:inst1.q[5]
d7[6] <= lpm_shiftreg2:inst1.q[6]
d7[7] <= lpm_shiftreg2:inst1.q[7]
d7[8] <= lpm_shiftreg2:inst1.q[8]
d7[9] <= lpm_shiftreg2:inst1.q[9]
d7[10] <= lpm_shiftreg2:inst1.q[10]
d7[11] <= lpm_shiftreg2:inst1.q[11]
d7[12] <= lpm_shiftreg2:inst1.q[12]
d7[13] <= lpm_shiftreg2:inst1.q[13]
d7[14] <= lpm_shiftreg2:inst1.q[14]
d7[15] <= lpm_shiftreg2:inst1.q[15]
dooo => lpm_shiftreg2:inst1.shiftin
q[0] <= q~0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q~1.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q~2.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q~3.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q~4.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q~5.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q~6.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q~7.DB_MAX_OUTPUT_PORT_TYPE
q[8] <= q~8.DB_MAX_OUTPUT_PORT_TYPE
q[9] <= q~9.DB_MAX_OUTPUT_PORT_TYPE
q[10] <= q~10.DB_MAX_OUTPUT_PORT_TYPE
q[11] <= q~11.DB_MAX_OUTPUT_PORT_TYPE
q[12] <= q~12.DB_MAX_OUTPUT_PORT_TYPE
q[13] <= q~13.DB_MAX_OUTPUT_PORT_TYPE
q[14] <= q~14.DB_MAX_OUTPUT_PORT_TYPE
q[15] <= q~15.DB_MAX_OUTPUT_PORT_TYPE
addr_r[0] => 74138:inst70.A
addr_r[0] => altsyncram0:inst33.rdaddress[0]
addr_r[0] => altsyncram0:inst34.rdaddress[0]
addr_r[0] => altsyncram0:inst31.rdaddress[0]
addr_r[0] => altsyncram0:inst32.rdaddress[0]
addr_r[0] => altsyncram0:inst29.rdaddress[0]
addr_r[0] => altsyncram0:inst30.rdaddress[0]
addr_r[0] => altsyncram0:inst26.rdaddress[0]
addr_r[0] => altsyncram0:inst28.rdaddress[0]
addr_r[1] => 74138:inst70.B
addr_r[1] => altsyncram0:inst33.rdaddress[1]
addr_r[1] => altsyncram0:inst34.rdaddress[1]
addr_r[1] => altsyncram0:inst31.rdaddress[1]
addr_r[1] => altsyncram0:inst32.rdaddress[1]
addr_r[1] => altsyncram0:inst29.rdaddress[1]
addr_r[1] => altsyncram0:inst30.rdaddress[1]
addr_r[1] => altsyncram0:inst26.rdaddress[1]
addr_r[1] => altsyncram0:inst28.rdaddress[1]
addr_r[2] => 74138:inst70.C
addr_r[2] => altsyncram0:inst33.rdaddress[2]
addr_r[2] => altsyncram0:inst34.rdaddress[2]
addr_r[2] => altsyncram0:inst31.rdaddress[2]
addr_r[2] => altsyncram0:inst32.rdaddress[2]
addr_r[2] => altsyncram0:inst29.rdaddress[2]
addr_r[2] => altsyncram0:inst30.rdaddress[2]
addr_r[2] => altsyncram0:inst26.rdaddress[2]
addr_r[2] => altsyncram0:inst28.rdaddress[2]
addr_r[3] => 74138:inst70.G1
addr_r[3] => inst.IN0
cs => altsyncram0:inst33.wren
cs => altsyncram0:inst34.wren
cs => altsyncram0:inst31.wren
cs => altsyncram0:inst32.wren
cs => altsyncram0:inst29.wren
cs => altsyncram0:inst30.wren
cs => altsyncram0:inst26.wren
cs => altsyncram0:inst28.wren
rden => altsyncram0:inst33.rden
rden => altsyncram0:inst34.rden
rden => altsyncram0:inst31.rden
rden => altsyncram0:inst32.rden
rden => altsyncram0:inst29.rden
rden => altsyncram0:inst30.rden
rden => altsyncram0:inst26.rden
rden => altsyncram0:inst28.rden
rdclk => altsyncram0:inst33.rdclock
rdclk => altsyncram0:inst34.rdclock
rdclk => altsyncram0:inst31.rdclock
rdclk => altsyncram0:inst32.rdclock
rdclk => altsyncram0:inst29.rdclock
rdclk => altsyncram0:inst30.rdclock
rdclk => altsyncram0:inst26.rdclock
rdclk => altsyncram0:inst28.rdclock
addr[0] => altsyncram0:inst33.wraddress[0]
addr[0] => altsyncram0:inst34.wraddress[0]
addr[0] => altsyncram0:inst31.wraddress[0]
addr[0] => altsyncram0:inst32.wraddress[0]
addr[0] => altsyncram0:inst29.wraddress[0]
addr[0] => altsyncram0:inst30.wraddress[0]