ads7844.tan.summary

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.472 ns
From           : rden
To             : d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a15~portb_address_reg2
From Clock     : --
To Clock       : rdclk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.898 ns
From           : d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a6~portb_address_reg2
To             : q[5]
From Clock     : rdclk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 15.189 ns
From           : addr_r[0]
To             : q[10]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.994 ns
From           : addr_r[0]
To             : d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated|ram_block1a11~portb_address_reg0
From Clock     : --
To Clock       : rdclk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 95.27 MHz ( period = 10.496 ns )
From           : cs_pulse:inst5|inst6
To             : to_ad:inst4|74165b:inst|96
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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