fq.vhd

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 6.0 (Build Build 178 04/27/2006)
-- Created on Tue Jul 24 14:54:29 2007

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


--  Entity Declaration

ENTITY fq IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		clk : IN STD_LOGIC;
		clk1 : OUT STD_LOGIC
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END fq;


--  Architecture Body

ARCHITECTURE fq_ar OF fq IS
signal clk_temp :std_logic;
begin 
process (clk)  
variable counter:integer range 0 to 15;
constant md:integer:=1; 
begin
    if clk'event and clk='1' then 
       if counter=md then 
         counter:=0;
         clk_temp<=not clk_temp;
       else   
         counter:=counter+1;
       end if;
    end if;
end process;
clk1<=clk_temp;
END fq_ar;