lpm_shiftreg1.cmp

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

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component lpm_shiftreg1
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
end component;