fq_cs.vhd

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 6.0 (Build Build 178 04/27/2006)
-- Created on Tue Jul 24 17:26:29 2007

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY fq_cs IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		clk2 : IN STD_LOGIC;
		cs_all : IN STD_LOGIC;
		cs : inout STD_LOGIC;
		stld:out std_logic
		
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END fq_cs;


--  Architecture Body

ARCHITECTURE fq_cs_architecture OF fq_cs IS
component dff_2
   port(d:in std_logic;
        clk:in std_logic;
        q:out std_logic);
end component;
signal temp1,temp2:std_logic:='0';
--signal cs_ad_t:std_logic:='0';
--signal cs_gg:std_logic:='1';
begin

       u1:dff_2  port map(d=>cs,clk=>clk2,q=>temp1);
       u2:dff_2 port map(d=>temp1,clk=>clk2,q=>temp2);
 


process(cs_all,clk2)
variable q:integer range 0 to 23;
--variable delay:integer range 0 to 3:=0;
begin
 if cs_all='1' then cs<='0';
    q:=0;
 elsif clk2'event and clk2='1' then
      if q<23 then 
         cs<='0';
          --if q<3 then
           --if delay<3 then
             -- cs_gg<='1';
            --  delay:=delay+1;
        --   else 
       --       cs_gg<='0';
        --      delay:=0;
        --   end if;
       --   end if;           
         q:=q+1;
      else
      cs<='1';
    --  cs_gg<='1';
      q:=0;
      end if;
 end if;
end process;



--process(clk2,cs)
--variable cs_count:integer range 0 to 2:=0;
--constant md:integer:=2; 
   --begin
    
      --if clk2'event and clk2='0' then 
         --if cs='1'  then
           --cs_ad_t<='1';
                 
            -- if cs_count=md then
              -- cs_ad_t<='0';
              -- cs_count:=0;
        --     else
     --          cs_count:=cs_count+1;
    --         end if;
  --      end if;
--   end if;
-- end process;
 
--cs_ad<=cs_ad_t;  
stld<=not temp2;   
--cs_ad<=cs_gg;    
   


END fq_cs_architecture;