cs_wide.vhd

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 6.0 (Build Build 178 04/27/2006)
-- Created on Thu Jul 26 20:15:31 2007

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY cs_wide IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		ena : IN STD_LOGIC;
		clrn : IN STD_LOGIC;
		clk : IN STD_LOGIC;
		cai : IN STD_LOGIC;
		co : OUT STD_LOGIC
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END cs_wide;


--  Architecture Body

ARCHITECTURE cs_wide_architecture OF cs_wide IS

begin

process(clk,clrn)
variable q:integer range 0 to 2;
  begin
    if (clrn='0') then 
       q:=0;
       co<='0';
    elsif (clk'event and clk='1') then
       if ena='1' then
          if q<2 then 
            q:=q+1;
            co<='0';
          else
            q:=0;
            co<='1';
          end if;
       else
          q:=q;          
       end if;
    end if;        
  end process;  

END cs_wide_architecture;