timer.out

8051的verilog源代码

Loading snapshot worklib.oc8051_tb:v .................... Done
ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc
ncsim> run

Warning!  some objects excluded from $dumpvars due to -access -R
            File: /home/simont/oc8051/bench/verilog/oc8051_tb.v, line = 154, pos = 16
           Scope: oc8051_tb
            Time: 0 FS + 0

time                    1 step           0: pass
time                36056 step           1: pass
time                36156 step           2: pass
time                36246 step           3: pass

 Done!
Simulation complete via $finish(1) at time 36246 NS + 2
/home/simont/oc8051/bench/verilog/oc8051_tb.v:148       $finish;
ncsim> exit