led.tan.qmsg

以两种结构编写的VHDL驱动LED 已通过调试

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1 " "Info: Detected ripple clock \"clk1\" as buffer" {  } { { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 12 -1 0 } } { "d:/quartusii/win/Assignment Editor.qase" "" { Assignment "d:/quartusii/win/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register \\p0:count\[1\] register \\p0:count\[9\] 57.8 MHz 17.3 ns Internal " "Info: Clock \"clk\" has Internal fmax of 57.8 MHz between source register \"\\p0:count\[1\]\" and destination register \"\\p0:count\[9\]\" (period= 17.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.800 ns + Longest register register " "Info: + Longest register to register delay is 12.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\p0:count\[1\] 1 REG LC21 28 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 28; REG Node = '\\p0:count\[1\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { \p0:count[1] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(4.400 ns) 7.100 ns lpm_add_sub:Add0\|addcore:adder\[1\]\|a_csnbuffer:result_node\|sout_node\[1\]~19 2 COMB LC27 1 " "Info: 2: + IC(2.700 ns) + CELL(4.400 ns) = 7.100 ns; Loc. = LC27; Fanout = 1; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\[1\]\|a_csnbuffer:result_node\|sout_node\[1\]~19'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "7.100 ns" { \p0:count[1] lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~19 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/quartusii/libraries/megafunctions/a_csnbuffer.tdf" 42 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.100 ns) 12.800 ns \\p0:count\[9\] 3 REG LC1 20 " "Info: 3: + IC(2.600 ns) + CELL(3.100 ns) = 12.800 ns; Loc. = LC1; Fanout = 20; REG Node = '\\p0:count\[9\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "5.700 ns" { lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~19 \p0:count[9] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns ( 58.59 % ) " "Info: Total cell delay = 7.500 ns ( 58.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.300 ns ( 41.41 % ) " "Info: Total interconnect delay = 5.300 ns ( 41.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "12.800 ns" { \p0:count[1] lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~19 \p0:count[9] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "12.800 ns" { \p0:count[1] lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~19 \p0:count[9] } { 0.000ns 2.700ns 2.600ns } { 0.000ns 4.400ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 21 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns \\p0:count\[9\] 2 REG LC1 20 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC1; Fanout = 20; REG Node = '\\p0:count\[9\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "0.900 ns" { clk \p0:count[9] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk \p0:count[9] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out \p0:count[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 21 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns \\p0:count\[1\] 2 REG LC21 28 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC21; Fanout = 28; REG Node = '\\p0:count\[1\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "0.900 ns" { clk \p0:count[1] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk \p0:count[1] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out \p0:count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk \p0:count[9] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out \p0:count[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk \p0:count[1] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out \p0:count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "12.800 ns" { \p0:count[1] lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~19 \p0:count[9] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "12.800 ns" { \p0:count[1] lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~19 \p0:count[9] } { 0.000ns 2.700ns 2.600ns } { 0.000ns 4.400ns 3.100ns } } } { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk \p0:count[9] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out \p0:count[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "3.400 ns" { clk \p0:count[1] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "3.400 ns" { clk clk~out \p0:count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "temp\[1\] rest clk 0.200 ns register " "Info: tsu for register \"temp\[1\]\" (data pin = \"rest\", clock pin = \"clk\") is 0.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.200 ns + Longest pin register " "Info: + Longest pin to register delay is 7.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns rest 1 PIN PIN_37 24 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_37; Fanout = 24; PIN Node = 'rest'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { rest } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 7.200 ns temp\[1\] 2 REG LC49 2 " "Info: 2: + IC(2.700 ns) + CELL(3.100 ns) = 7.200 ns; Loc. = LC49; Fanout = 2; REG Node = 'temp\[1\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "5.800 ns" { rest temp[1] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 62.50 % ) " "Info: Total cell delay = 4.500 ns ( 62.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 37.50 % ) " "Info: Total interconnect delay = 2.700 ns ( 37.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "7.200 ns" { rest temp[1] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "7.200 ns" { rest rest~out temp[1] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 21 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns clk1 2 REG LC3 17 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC3; Fanout = 17; REG Node = 'clk1'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns temp\[1\] 3 REG LC49 2 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC49; Fanout = 2; REG Node = 'temp\[1\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "4.900 ns" { clk1 temp[1] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 72.73 % ) " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 27.27 % ) " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clk clk1 temp[1] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clk clk~out clk1 temp[1] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "7.200 ns" { rest temp[1] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "7.200 ns" { rest rest~out temp[1] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 3.100ns } } } { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clk clk1 temp[1] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clk clk~out clk1 temp[1] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[7\] q\[7\]~reg0 13.100 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[7\]\" through register \"q\[7\]~reg0\" is 13.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 21 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns clk1 2 REG LC3 17 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC3; Fanout = 17; REG Node = 'clk1'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns q\[7\]~reg0 3 REG LC59 2 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC59; Fanout = 2; REG Node = 'q\[7\]~reg0'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "4.900 ns" { clk1 q[7]~reg0 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 72.73 % ) " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 27.27 % ) " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clk clk1 q[7]~reg0 } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clk clk~out clk1 q[7]~reg0 } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.600 ns + Longest register pin " "Info: + Longest register to pin delay is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[7\]~reg0 1 REG LC59 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC59; Fanout = 2; REG Node = 'q\[7\]~reg0'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { q[7]~reg0 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns q\[7\] 2 PIN PIN_30 0 " "Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'q\[7\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "1.600 ns" { q[7]~reg0 q[7] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "1.600 ns" { q[7]~reg0 q[7] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "1.600 ns" { q[7]~reg0 q[7] } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clk clk1 q[7]~reg0 } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clk clk~out clk1 q[7]~reg0 } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "1.600 ns" { q[7]~reg0 q[7] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "1.600 ns" { q[7]~reg0 q[7] } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "temp\[1\] rest clk 4.000 ns register " "Info: th for register \"temp\[1\]\" (data pin = \"rest\", clock pin = \"clk\") is 4.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 21 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns clk1 2 REG LC3 17 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC3; Fanout = 17; REG Node = 'clk1'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns temp\[1\] 3 REG LC49 2 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC49; Fanout = 2; REG Node = 'temp\[1\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "4.900 ns" { clk1 temp[1] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 72.73 % ) " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 27.27 % ) " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clk clk1 temp[1] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clk clk~out clk1 temp[1] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns rest 1 PIN PIN_37 24 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_37; Fanout = 24; PIN Node = 'rest'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { rest } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 7.200 ns temp\[1\] 2 REG LC49 2 " "Info: 2: + IC(2.700 ns) + CELL(3.100 ns) = 7.200 ns; Loc. = LC49; Fanout = 2; REG Node = 'temp\[1\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "5.800 ns" { rest temp[1] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/quartusii/led/led.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 62.50 % ) " "Info: Total cell delay = 4.500 ns ( 62.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 37.50 % ) " "Info: Total interconnect delay = 2.700 ns ( 37.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "7.200 ns" { rest temp[1] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "7.200 ns" { rest rest~out temp[1] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clk clk1 temp[1] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clk clk~out clk1 temp[1] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "7.200 ns" { rest temp[1] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "7.200 ns" { rest rest~out temp[1] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 3.100ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 17 12:57:41 2008 " "Info: Processing ended: Thu Jan 17 12:57:41 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}