led.tan.rpt

以两种结构编写的VHDL驱动LED 已通过调试

+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; 4.000 ns  ; rest ; temp[1]   ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; temp[0]   ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; temp[7]   ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; temp[6]   ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; temp[5]   ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; temp[4]   ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; temp[3]   ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; temp[2]   ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; q[6]~reg0 ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; q[5]~reg0 ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; q[4]~reg0 ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; 4.000 ns  ; rest ; q[7]~reg0 ; clk      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jan 17 12:57:41 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off led -c led
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk1" as buffer
Info: Clock "clk" has Internal fmax of 57.8 MHz between source register "\p0:count[1]" and destination register "\p0:count[9]" (period= 17.3 ns)
    Info: + Longest register to register delay is 12.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 28; REG Node = '\p0:count[1]'
        Info: 2: + IC(2.700 ns) + CELL(4.400 ns) = 7.100 ns; Loc. = LC27; Fanout = 1; COMB Node = 'lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~19'
        Info: 3: + IC(2.600 ns) + CELL(3.100 ns) = 12.800 ns; Loc. = LC1; Fanout = 20; REG Node = '\p0:count[9]'
        Info: Total cell delay = 7.500 ns ( 58.59 % )
        Info: Total interconnect delay = 5.300 ns ( 41.41 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC1; Fanout = 20; REG Node = '\p0:count[9]'
            Info: Total cell delay = 3.400 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC21; Fanout = 28; REG Node = '\p0:count[1]'
            Info: Total cell delay = 3.400 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: tsu for register "temp[1]" (data pin = "rest", clock pin = "clk") is 0.200 ns
    Info: + Longest pin to register delay is 7.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_37; Fanout = 24; PIN Node = 'rest'
        Info: 2: + IC(2.700 ns) + CELL(3.100 ns) = 7.200 ns; Loc. = LC49; Fanout = 2; REG Node = 'temp[1]'
        Info: Total cell delay = 4.500 ns ( 62.50 % )
        Info: Total interconnect delay = 2.700 ns ( 37.50 % )
    Info: + Micro setup delay of destination is 2.900 ns
    Info: - Shortest clock path from clock "clk" to destination register is 9.900 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC3; Fanout = 17; REG Node = 'clk1'
        Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC49; Fanout = 2; REG Node = 'temp[1]'
        Info: Total cell delay = 7.200 ns ( 72.73 % )
        Info: Total interconnect delay = 2.700 ns ( 27.27 % )
Info: tco from clock "clk" to destination pin "q[7]" through register "q[7]~reg0" is 13.100 ns
    Info: + Longest clock path from clock "clk" to source register is 9.900 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC3; Fanout = 17; REG Node = 'clk1'
        Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC59; Fanout = 2; REG Node = 'q[7]~reg0'
        Info: Total cell delay = 7.200 ns ( 72.73 % )
        Info: Total interconnect delay = 2.700 ns ( 27.27 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 1.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC59; Fanout = 2; REG Node = 'q[7]~reg0'
        Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'q[7]'
        Info: Total cell delay = 1.600 ns ( 100.00 % )
Info: th for register "temp[1]" (data pin = "rest", clock pin = "clk") is 4.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 9.900 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 21; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC3; Fanout = 17