led.vhd

以两种结构编写的VHDL驱动LED 已通过调试

library ieee;
use ieee.std_logic_1164.all;
entity led is
port(clkq:in std_logic;
     rst:in std_logic;
      q1:out std_logic_vector(0 to 7));
end led;
architecture structure of led is 
component ledx is  
   port(clk:out std_logic;main_clk:in std_logic);
end component ledx; 
component ledy is  
   port(q:out std_logic_vector(0 to 7);rst:in std_logic;clkin:in std_logic);
end component ledy;
signal sig:std_logic; 
begin
u1:component ledx
port map(clk=>sig,main_clk=>clkq);
u2:component ledy
port map(clkin=>sig,rst=>rst,q=>q1);
end structure;