ledx.vhd

以两种结构编写的VHDL驱动LED 已通过调试

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ledx is
port(clk:out std_logic;
	main_clk:in std_logic);
end ledx;
architecture behave of ledx is
begin
process(main_clk)
variable temp:std_logic_vector(19 downto 0);
	begin
		if rising_edge(main_clk) then
			temp:=temp+1;
		end if;
		if(temp="11111111111111111111")then
		    temp:="00000000000000000000";
		end if;
		 clk<=temp(19);
end process;
end behave;