ledy.vhd

来自「以两种结构编写的VHDL驱动LED 已通过调试」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all;
entity ledy is
port(clkin:in std_logic;
	 rst:in std_logic;
     q:out std_logic_vector(0 to 7));
end ledy;
architecture behave of ledy is
begin
process(clkin,rst)
variable temp:std_logic_vector(0 to 7);
begin

if(clkin'event and clkin='1')then
    if(rst='0')then temp:="00000001";
    else temp:=temp(7)&temp(0 to 6);
end if;
end if;
    q<=temp;
end process;
end behave;