led.tan.qmsg

以两种结构编写的VHDL驱动LED 已通过调试

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkq register ledy:u2\|temp\[7\] register ledy:u2\|temp\[0\] 57.8 MHz 17.3 ns Internal " "Info: Clock \"clkq\" has Internal fmax of 57.8 MHz between source register \"ledy:u2\|temp\[7\]\" and destination register \"ledy:u2\|temp\[0\]\" (period= 17.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.700 ns + Longest register register " "Info: + Longest register to register delay is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ledy:u2\|temp\[7\] 1 REG LC59 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC59; Fanout = 2; REG Node = 'ledy:u2\|temp\[7\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { ledy:u2|temp[7] } "NODE_NAME" } } { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.100 ns) 5.700 ns ledy:u2\|temp\[0\] 2 REG LC38 2 " "Info: 2: + IC(2.600 ns) + CELL(3.100 ns) = 5.700 ns; Loc. = LC38; Fanout = 2; REG Node = 'ledy:u2\|temp\[0\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "5.700 ns" { ledy:u2|temp[7] ledy:u2|temp[0] } "NODE_NAME" } } { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns ( 54.39 % ) " "Info: Total cell delay = 3.100 ns ( 54.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 45.61 % ) " "Info: Total interconnect delay = 2.600 ns ( 45.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "5.700 ns" { ledy:u2|temp[7] ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "5.700 ns" { ledy:u2|temp[7] ledy:u2|temp[0] } { 0.000ns 2.600ns } { 0.000ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-7.100 ns - Smallest " "Info: - Smallest clock skew is -7.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkq destination 9.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clkq\" to destination register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clkq 1 CLK PIN_87 20 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 20; CLK Node = 'clkq'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { clkq } "NODE_NAME" } } { "led.vhd" "" { Text "D:/led/led.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns ledx:u1\|temp\[19\] 2 REG LC36 10 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC36; Fanout = 10; REG Node = 'ledx:u1\|temp\[19\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clkq ledx:u1|temp[19] } "NODE_NAME" } } { "ledx.vhd" "" { Text "D:/led/ledx.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns ledy:u2\|temp\[0\] 3 REG LC38 2 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC38; Fanout = 2; REG Node = 'ledy:u2\|temp\[0\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "4.900 ns" { ledx:u1|temp[19] ledy:u2|temp[0] } "NODE_NAME" } } { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 72.73 % ) " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 27.27 % ) " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clkq ledx:u1|temp[19] ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clkq clkq~out ledx:u1|temp[19] ledy:u2|temp[0] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkq source 17.000 ns - Longest register " "Info: - Longest clock path from clock \"clkq\" to source register is 17.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clkq 1 CLK PIN_87 20 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 20; CLK Node = 'clkq'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { clkq } "NODE_NAME" } } { "led.vhd" "" { Text "D:/led/led.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns ledx:u1\|temp\[9\] 2 REG LC6 13 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC6; Fanout = 13; REG Node = 'ledx:u1\|temp\[9\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clkq ledx:u1|temp[9] } "NODE_NAME" } } { "ledx.vhd" "" { Text "D:/led/ledx.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(4.400 ns) 12.100 ns ledx:u1\|clk~73bal 3 COMB LC40 8 " "Info: 3: + IC(2.700 ns) + CELL(4.400 ns) = 12.100 ns; Loc. = LC40; Fanout = 8; COMB Node = 'ledx:u1\|clk~73bal'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "7.100 ns" { ledx:u1|temp[9] ledx:u1|clk~73bal } "NODE_NAME" } } { "ledx.vhd" "" { Text "D:/led/ledx.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 17.000 ns ledy:u2\|temp\[7\] 4 REG LC59 2 " "Info: 4: + IC(2.700 ns) + CELL(2.200 ns) = 17.000 ns; Loc. = LC59; Fanout = 2; REG Node = 'ledy:u2\|temp\[7\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "4.900 ns" { ledx:u1|clk~73bal ledy:u2|temp[7] } "NODE_NAME" } } { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.600 ns ( 68.24 % ) " "Info: Total cell delay = 11.600 ns ( 68.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.400 ns ( 31.76 % ) " "Info: Total interconnect delay = 5.400 ns ( 31.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "17.000 ns" { clkq ledx:u1|temp[9] ledx:u1|clk~73bal ledy:u2|temp[7] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "17.000 ns" { clkq clkq~out ledx:u1|temp[9] ledx:u1|clk~73bal ledy:u2|temp[7] } { 0.000ns 0.000ns 0.000ns 2.700ns 2.700ns } { 0.000ns 2.500ns 2.500ns 4.400ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clkq ledx:u1|temp[19] ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clkq clkq~out ledx:u1|temp[19] ledy:u2|temp[0] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "17.000 ns" { clkq ledx:u1|temp[9] ledx:u1|clk~73bal ledy:u2|temp[7] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "17.000 ns" { clkq clkq~out ledx:u1|temp[9] ledx:u1|clk~73bal ledy:u2|temp[7] } { 0.000ns 0.000ns 0.000ns 2.700ns 2.700ns } { 0.000ns 2.500ns 2.500ns 4.400ns 2.200ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "5.700 ns" { ledy:u2|temp[7] ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "5.700 ns" { ledy:u2|temp[7] ledy:u2|temp[0] } { 0.000ns 2.600ns } { 0.000ns 3.100ns } } } { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clkq ledx:u1|temp[19] ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clkq clkq~out ledx:u1|temp[19] ledy:u2|temp[0] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "17.000 ns" { clkq ledx:u1|temp[9] ledx:u1|clk~73bal ledy:u2|temp[7] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "17.000 ns" { clkq clkq~out ledx:u1|temp[9] ledx:u1|clk~73bal ledy:u2|temp[7] } { 0.000ns 0.000ns 0.000ns 2.700ns 2.700ns } { 0.000ns 2.500ns 2.500ns 4.400ns 2.200ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clkq 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"clkq\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "ledy:u2\|temp\[7\] ledy:u2\|temp\[0\] clkq 1.1 ns " "Info: Found hold time violation between source  pin or register \"ledy:u2\|temp\[7\]\" and destination pin or register \"ledy:u2\|temp\[0\]\" for clock \"clkq\" (Hold time is 1.1 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.100 ns + Largest " "Info: + Largest clock skew is 7.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkq destination 17.000 ns + Longest register " "Info: + Longest clock path from clock \"clkq\" to destination register is 17.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clkq 1 CLK PIN_87 20 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 20; CLK Node = 'clkq'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { clkq } "NODE_NAME" } } { "led.vhd" "" { Text "D:/led/led.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns ledx:u1\|temp\[9\] 2 REG LC6 13 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC6; Fanout = 13; REG Node = 'ledx:u1\|temp\[9\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clkq ledx:u1|temp[9] } "NODE_NAME" } } { "ledx.vhd" "" { Text "D:/led/ledx.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(4.400 ns) 12.100 ns ledx:u1\|clk~73bal 3 COMB LC40 8 " "Info: 3: + IC(2.700 ns) + CELL(4.400 ns) = 12.100 ns; Loc. = LC40; Fanout = 8; COMB Node = 'ledx:u1\|clk~73bal'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "7.100 ns" { ledx:u1|temp[9] ledx:u1|clk~73bal } "NODE_NAME" } } { "ledx.vhd" "" { Text "D:/led/ledx.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 17.000 ns ledy:u2\|temp\[0\] 4 REG LC38 2 " "Info: 4: + IC(2.700 ns) + CELL(2.200 ns) = 17.000 ns; Loc. = LC38; Fanout = 2; REG Node = 'ledy:u2\|temp\[0\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "4.900 ns" { ledx:u1|clk~73bal ledy:u2|temp[0] } "NODE_NAME" } } { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.600 ns ( 68.24 % ) " "Info: Total cell delay = 11.600 ns ( 68.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.400 ns ( 31.76 % ) " "Info: Total interconnect delay = 5.400 ns ( 31.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "17.000 ns" { clkq ledx:u1|temp[9] ledx:u1|clk~73bal ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "17.000 ns" { clkq clkq~out ledx:u1|temp[9] ledx:u1|clk~73bal ledy:u2|temp[0] } { 0.000ns 0.000ns 0.000ns 2.700ns 2.700ns } { 0.000ns 2.500ns 2.500ns 4.400ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkq source 9.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clkq\" to source register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clkq 1 CLK PIN_87 20 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 20; CLK Node = 'clkq'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { clkq } "NODE_NAME" } } { "led.vhd" "" { Text "D:/led/led.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns ledx:u1\|temp\[19\] 2 REG LC36 10 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC36; Fanout = 10; REG Node = 'ledx:u1\|temp\[19\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clkq ledx:u1|temp[19] } "NODE_NAME" } } { "ledx.vhd" "" { Text "D:/led/ledx.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns ledy:u2\|temp\[7\] 3 REG LC59 2 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC59; Fanout = 2; REG Node = 'ledy:u2\|temp\[7\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "4.900 ns" { ledx:u1|temp[19] ledy:u2|temp[7] } "NODE_NAME" } } { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 72.73 % ) " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 27.27 % ) " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clkq ledx:u1|temp[19] ledy:u2|temp[7] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clkq clkq~out ledx:u1|temp[19] ledy:u2|temp[7] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "17.000 ns" { clkq ledx:u1|temp[9] ledx:u1|clk~73bal ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "17.000 ns" { clkq clkq~out ledx:u1|temp[9] ledx:u1|clk~73bal ledy:u2|temp[0] } { 0.000ns 0.000ns 0.000ns 2.700ns 2.700ns } { 0.000ns 2.500ns 2.500ns 4.400ns 2.200ns } } } { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clkq ledx:u1|temp[19] ledy:u2|temp[7] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clkq clkq~out ledx:u1|temp[19] ledy:u2|temp[7] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns - " "Info: - Micro clock to output delay of source is 1.600 ns" {  } { { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.700 ns - Shortest register register " "Info: - Shortest register to register delay is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ledy:u2\|temp\[7\] 1 REG LC59 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC59; Fanout = 2; REG Node = 'ledy:u2\|temp\[7\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { ledy:u2|temp[7] } "NODE_NAME" } } { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.100 ns) 5.700 ns ledy:u2\|temp\[0\] 2 REG LC38 2 " "Info: 2: + IC(2.600 ns) + CELL(3.100 ns) = 5.700 ns; Loc. = LC38; Fanout = 2; REG Node = 'ledy:u2\|temp\[0\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "5.700 ns" { ledy:u2|temp[7] ledy:u2|temp[0] } "NODE_NAME" } } { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns ( 54.39 % ) " "Info: Total cell delay = 3.100 ns ( 54.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 45.61 % ) " "Info: Total interconnect delay = 2.600 ns ( 45.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "5.700 ns" { ledy:u2|temp[7] ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "5.700 ns" { ledy:u2|temp[7] ledy:u2|temp[0] } { 0.000ns 2.600ns } { 0.000ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "17.000 ns" { clkq ledx:u1|temp[9] ledx:u1|clk~73bal ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "17.000 ns" { clkq clkq~out ledx:u1|temp[9] ledx:u1|clk~73bal ledy:u2|temp[0] } { 0.000ns 0.000ns 0.000ns 2.700ns 2.700ns } { 0.000ns 2.500ns 2.500ns 4.400ns 2.200ns } } } { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clkq ledx:u1|temp[19] ledy:u2|temp[7] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clkq clkq~out ledx:u1|temp[19] ledy:u2|temp[7] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "5.700 ns" { ledy:u2|temp[7] ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "5.700 ns" { ledy:u2|temp[7] ledy:u2|temp[0] } { 0.000ns 2.600ns } { 0.000ns 3.100ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ledy:u2\|temp\[0\] rst clkq 0.200 ns register " "Info: tsu for register \"ledy:u2\|temp\[0\]\" (data pin = \"rst\", clock pin = \"clkq\") is 0.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.200 ns + Longest pin register " "Info: + Longest pin to register delay is 7.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns rst 1 PIN PIN_37 8 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_37; Fanout = 8; PIN Node = 'rst'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "led.vhd" "" { Text "D:/led/led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 7.200 ns ledy:u2\|temp\[0\] 2 REG LC38 2 " "Info: 2: + IC(2.700 ns) + CELL(3.100 ns) = 7.200 ns; Loc. = LC38; Fanout = 2; REG Node = 'ledy:u2\|temp\[0\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "5.800 ns" { rst ledy:u2|temp[0] } "NODE_NAME" } } { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 62.50 % ) " "Info: Total cell delay = 4.500 ns ( 62.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 37.50 % ) " "Info: Total interconnect delay = 2.700 ns ( 37.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "7.200 ns" { rst ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "7.200 ns" { rst rst~out ledy:u2|temp[0] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkq destination 9.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clkq\" to destination register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clkq 1 CLK PIN_87 20 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 20; CLK Node = 'clkq'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "" { clkq } "NODE_NAME" } } { "led.vhd" "" { Text "D:/led/led.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns ledx:u1\|temp\[19\] 2 REG LC36 10 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC36; Fanout = 10; REG Node = 'ledx:u1\|temp\[19\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clkq ledx:u1|temp[19] } "NODE_NAME" } } { "ledx.vhd" "" { Text "D:/led/ledx.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns ledy:u2\|temp\[0\] 3 REG LC38 2 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC38; Fanout = 2; REG Node = 'ledy:u2\|temp\[0\]'" {  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "4.900 ns" { ledx:u1|temp[19] ledy:u2|temp[0] } "NODE_NAME" } } { "ledy.vhd" "" { Text "D:/led/ledy.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 72.73 % ) " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 27.27 % ) " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clkq ledx:u1|temp[19] ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clkq clkq~out ledx:u1|temp[19] ledy:u2|temp[0] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "7.200 ns" { rst ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "7.200 ns" { rst rst~out ledy:u2|temp[0] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 1.400ns 3.100ns } } } { "d:/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/win/TimingClosureFloorplan.fld" "" "9.900 ns" { clkq ledx:u1|temp[19] ledy:u2|temp[0] } "NODE_NAME" } } { "d:/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartusii/win/Technology_Viewer.qrui" "9.900 ns" { clkq clkq~out ledx:u1|temp[19] ledy:u2|temp[0] } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}