led.tan.summary

以两种结构编写的VHDL驱动LED 已通过调试

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 0.200 ns
From           : rst
To             : ledy:u2|temp[1]
From Clock     : --
To Clock       : clkq
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 20.200 ns
From           : ledy:u2|temp[0]
To             : q1[0]
From Clock     : clkq
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 11.100 ns
From           : rst
To             : ledy:u2|temp[1]
From Clock     : --
To Clock       : clkq
Failed Paths   : 0

Type           : Clock Setup: 'clkq'
Slack          : N/A
Required Time  : None
Actual Time    : 57.80 MHz ( period = 17.300 ns )
From           : ledy:u2|temp[0]
To             : ledy:u2|temp[1]
From Clock     : clkq
To Clock       : clkq
Failed Paths   : 0

Type           : Clock Hold: 'clkq'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : ledy:u2|temp[7]
To             : ledy:u2|temp[0]
From Clock     : clkq
To Clock       : clkq
Failed Paths   : 8

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 8

--------------------------------------------------------------------------------------