led.tan.rpt

以两种结构编写的VHDL驱动LED 已通过调试

; Not operational: Clock Skew > Data Delay ; ledy:u2|temp[2] ; ledy:u2|temp[3] ; clkq       ; clkq     ; None                       ; None                       ; 5.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; ledy:u2|temp[1] ; ledy:u2|temp[2] ; clkq       ; clkq     ; None                       ; None                       ; 5.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; ledy:u2|temp[0] ; ledy:u2|temp[1] ; clkq       ; clkq     ; None                       ; None                       ; 5.700 ns                 ;
+------------------------------------------+-----------------+-----------------+------------+----------+----------------------------+----------------------------+--------------------------+


+-----------------------------------------------------------------------+
; tsu                                                                   ;
+-------+--------------+------------+------+-----------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To              ; To Clock ;
+-------+--------------+------------+------+-----------------+----------+
; N/A   ; None         ; 0.200 ns   ; rst  ; ledy:u2|temp[0] ; clkq     ;
; N/A   ; None         ; 0.200 ns   ; rst  ; ledy:u2|temp[7] ; clkq     ;
; N/A   ; None         ; 0.200 ns   ; rst  ; ledy:u2|temp[6] ; clkq     ;
; N/A   ; None         ; 0.200 ns   ; rst  ; ledy:u2|temp[5] ; clkq     ;
; N/A   ; None         ; 0.200 ns   ; rst  ; ledy:u2|temp[4] ; clkq     ;
; N/A   ; None         ; 0.200 ns   ; rst  ; ledy:u2|temp[3] ; clkq     ;
; N/A   ; None         ; 0.200 ns   ; rst  ; ledy:u2|temp[2] ; clkq     ;
; N/A   ; None         ; 0.200 ns   ; rst  ; ledy:u2|temp[1] ; clkq     ;
+-------+--------------+------------+------+-----------------+----------+


+--------------------------------------------------------------------------+
; tco                                                                      ;
+-------+--------------+------------+-----------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From            ; To    ; From Clock ;
+-------+--------------+------------+-----------------+-------+------------+
; N/A   ; None         ; 20.200 ns  ; ledy:u2|temp[7] ; q1[7] ; clkq       ;
; N/A   ; None         ; 20.200 ns  ; ledy:u2|temp[6] ; q1[6] ; clkq       ;
; N/A   ; None         ; 20.200 ns  ; ledy:u2|temp[5] ; q1[5] ; clkq       ;
; N/A   ; None         ; 20.200 ns  ; ledy:u2|temp[4] ; q1[4] ; clkq       ;
; N/A   ; None         ; 20.200 ns  ; ledy:u2|temp[3] ; q1[3] ; clkq       ;
; N/A   ; None         ; 20.200 ns  ; ledy:u2|temp[2] ; q1[2] ; clkq       ;
; N/A   ; None         ; 20.200 ns  ; ledy:u2|temp[1] ; q1[1] ; clkq       ;
; N/A   ; None         ; 20.200 ns  ; ledy:u2|temp[0] ; q1[0] ; clkq       ;
+-------+--------------+------------+-----------------+-------+------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To              ; To Clock ;
+---------------+-------------+-----------+------+-----------------+----------+
; N/A           ; None        ; 11.100 ns ; rst  ; ledy:u2|temp[0] ; clkq     ;
; N/A           ; None        ; 11.100 ns ; rst  ; ledy:u2|temp[7] ; clkq     ;
; N/A           ; None        ; 11.100 ns ; rst  ; ledy:u2|temp[6] ; clkq     ;
; N/A           ; None        ; 11.100 ns ; rst  ; ledy:u2|temp[5] ; clkq     ;
; N/A           ; None        ; 11.100 ns ; rst  ; ledy:u2|temp[4] ; clkq     ;
; N/A           ; None        ; 11.100 ns ; rst  ; ledy:u2|temp[3] ; clkq     ;
; N/A           ; None        ; 11.100 ns ; rst  ; ledy:u2|temp[2] ; clkq     ;
; N/A           ; None        ; 11.100 ns ; rst  ; ledy:u2|temp[1] ; clkq     ;
+---------------+-------------+-----------+------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jan 17 13:57:31 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off led -c led
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkq" is an undefined clock
Warning: Found 21 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "ledx:u1|clk~73bal" as buffer
    Info: Detected ripple clock "ledx:u1|temp[16]" as buffer
    Info: Detected ripple clock "ledx:u1|temp[15]" as buffer
    Info: Detected ripple clock "ledx:u1|temp[8]" as buffer
    Info: Detected ripple clock "ledx:u1|temp[7]" as buffer
    Info: Detected ripple clock "ledx:u1|temp[1]" as buffer
    Info: Detected ripple clock "ledx:u1|temp[2]" as bu